LT3434_15 Datasheet, PDF (19/24 Pages) Linear Technology – High Voltage 3A, 200kHz Step-Down Switching Regulator with 100µA Quiescent Current

LT3434
APPLICATIO S I FOR ATIO
threshold during normal operation, the C_T pin will be
discharged and PG inactive, resulting in a non Power Good
cycle when SHDN is taken above its threshold. Figure 9
shows the power good operation with PGFB connected to
FB and the capacitance on C_T = 0.1µF. The PGFB pin has
a limited amount of driver capability and is susceptible to
V_OUT
500mV/DIV
PG
100k TO V_IN
V_CT
500mV/DIV
V_SHDN
2V/DIV
TIME (10ms/DIV)
3434 F09
Figure 9. Power Good
noise during start-up and Burst Mode operation. If erratic
operation occurs during these conditions a small filter
capacitor from the PGFB pin to ground will ensure proper
operation. Figure 10 shows several different configura-
tions for the LT3434 Power Good circuitry.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path, shown
in Figure 11, must be kept as short as possible. This is
implemented in the suggested layout of Figure 12. Short-
ening this path will also reduce the parasitic trace induc-
tance of approximately 25nH/inch. At switch off, this
parasitic inductance produces a flyback spike across the
PG at 80% V_OUT with 100ms Delay
V_IN
PG
LT3434
PGFB
FB
C_T
200k
153k
12k
100k
0.27µF
V_OUT = 3.3V
C_OUT
PG at V_IN > 4V with 100ms Delay
V_IN
PG
LT3434
PGFB
FB
C_T
200k
511k
200k
165k
100k
0.27µF
V_OUT = 3.3V
C_OUT
V_OUT Disconnect at 80% V_OUT
with 100ms Delay
V_OUT Disconnect 3.3V Logic Signal
with 100µs Delay
V_IN
200k
PG
V_IN
200k
PG
LT3434
PGFB
FB
C_T
153k
12k
100k
0.27µF
V_OUT = 3.3V
C_OUT
LT3434
PGFB
FB
C_T
C_OUT
866k
V_OUT = 12V
100k
270pF
3434 F10
Figure 10. Power Good Circuits
3434fb
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