LT1036_03 Datasheet, PDF (5/12 Pages) Linear Technology – Logic Controlled Regulator

TYPICAL PERFOR A CE CHARACTERISTICS
LT1036
Short-Circuit Current, 12V Output
5
T_J = 25°C
4
3
2
1
0
0 4 8 12 16 20 24 28 32
INPUT VOLTAGE (V)
LT1036M/1036C • TPC10
Output Switching Characteristics
15
12
CC_{OOUUT T}≤≤00.1.1µF
9
C_OUT = 1µF
6
C_OUT = 10µF
3
0
SEE APPLICATION SECTION
FOR FALL TIME INFORMATION
5
0
0 10 20 30 40 50 60 70 80 90
TIME (µs)
LT1036M/1036C • TPC11
Output Voltage Noise
200
180
160
140
120
100
80
60
40
20
0
100
MAIN (12V) OUTPUT
AUXILIARY
OUTPUT
300
1k
3k 10k 30k
BANDWIDTH (1 POLE) (Hz)
LT1036M/1036C • TPC12
APPLICATIO S I FOR ATIO
General Information
The LT1036 is a dual output regulator. The main 12V
output is capable of delivering up to 3A of load current and
can be shut down with a logic signal. The auxiliary 5V
output supplies a minimum of 75mA and is unaffected by
the logic signal. The outputs are trimmed to ± 2% initial
tolerance and exhibit excellent line and load regulation.
The logic control feature makes the LT1036 ideal for many
system applications where it is desirable to power-up a
portion of the system for a period of time, and then power
the system down during a standby operation. Applications
such as multiple power supply sequencing, elimination of
expensive AC and DC power switches, delayed start ap-
plications, switching 12V DC loads, and many others are
now easily accomplished.
Timing functions, such as delayed power-up or power-
down, can also be performed directly at the enable pin.
Because a logic low on the enable pin shuts down the main
regulator, feedback from output to enable can be used to
generate hysteresis or latching functions.
The low quiescent current drain of the LT1036 makes it
useful in battery-powered or battery back-up applications.
The enable pin can be used as a “low battery” detector or
to shut down major portions of system power, allowing
memory portions to continue to operate from the auxiliary
output. At low output currents, the auxiliary output will
regulate with input voltage typically as low as 6.2V, giving
maximum battery life.
Good design practice with all regulators is to bypass the
input and output terminals. A 2µF solid tantalum at the
input and at both outputs is suggested. For the applica-
tions which follow, the bypass capacitors are still recom-
mended, but for simplicity are not shown on the diagram.
It is also recommended that for maximum noise immunity
the voltage enable pin be tied high if it is unused. It can be
tied directly to V_IN, as shown in Figure 1, or to the auxiliary
Output. If the enable pin is left open, it will float to a high
logic level of approximately 1.6V and the main output
regulator will be at 12V.
The enable pin is fully protected against input voltages up
to 30V, even if the power input voltage is zero.
1036fa
5