LTC3576 Datasheet, PDF (41/48 Pages) Linear Technology – Switching Power Manager with USB On-the-Go + Triple Step-Down DC/DCs

APPLICATIONS INFORMATION
LTC3576/LTC3576-1
3576 F13
Figure 13. Higher Frequency Ground Current Follow Their
Incident Path. Slices in the Ground Plane Create Large Loop
Areas. The Large Loop Areas Increase the Inductance of the
Path Leading to Higher System Noise
it with V_OUT connected metal, which should generally be
less than one volt higher than IDGATE.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3576/LTC3576-1:
1. The Exposed Pad of the package (Pin 39) should con-
nect directly to a large ground plane to minimize thermal
and electrical impedance.
2. The traces connecting V_BUS, V_IN1, V_IN2, V_IN3 and V_IN of
the external step-down switching regulator to their respec-
tive decoupling capacitors should be as short as possible.
The GND side of these capacitors should connect directly
to the ground plane of the part. These capacitors provide
the AC current to the internal power MOSFETs and their
drivers. It is critical to minimize inductance from these
capacitors to the LTC3576/LTC3576-1 and external step-
down switching regulator.
3. Connections between the step-down switching regulator
(both internal and external) inductors and their respective
output capacitors should be kept as short as possible.
Use area fills whenever possible. This also applies to the
PowerPath switching regulator inductor and the output
capacitor on V_OUT. The GND side of the output capacitors
should connect directly to the thermal ground plane of
the part.
4. The switching power traces connecting SW, SW1,
SW2, SW3 and the switch node of the external step-down
switching regulator to their respective inductors should be
minimized to reduce radiated EMI and parasitic coupling.
Due to the large voltage swing of the switching nodes,
sensitive nodes such as the feedback nodes (FB1, FB2
and FB3) should be kept far away or shielded from the
switching nodes or poor performance could result.
5. Keep the feedback pin traces (FB1, FB2, FB3 and FB of
the external step-down switching regulator) as short as
possible. Minimize any parasitic capacitance between the
feedback traces and any switching node (i.e., SW, SW1,
SW2, SW3 and logic signals). If necessary shield the
feedback nodes with a GND trace
6. Connect V_IN1, V_IN2 and V_IN3 to V_OUT through a short
low impedance trace.
3576f
41