LTC3576 Datasheet, PDF (27/48 Pages) Linear Technology – Switching Power Manager with USB On-the-Go + Triple Step-Down DC/DCs

LTC3576/LTC3576-1
OPERATION
Thermal Regulation
To prevent thermal damage to the LTC3576/LTC3576-1 or
surrounding components, an internal thermal feedback
loop will automatically decrease the programmed charge
current if the die temperature rises to 105°C. This thermal
regulation technique protects the LTC3576/LTC3576-1
from excessive temperature due to high power operation
or high ambient thermal conditions, and allows the user
to push the limits of the power handling capability with
a given circuit board design. The benefit of the LTC3576/
LTC3576-1 thermal regulation loop is that charge current
can be set according to actual conditions rather than
worst-case conditions for a given application with the
assurance that the charger will automatically reduce the
current in worst-case conditions.
Overvoltage Protection
The LTC3576/LTC3576-1 can protect itself from the inadver-
tent application of excessive voltage to V_BUS or WALL with
just two external components: an N-channel MOSFET and
a 6.2k resistor. The maximum safe overvoltage magnitude
will be determined by the choice of the external MOSFET
and its associated drain breakdown voltage.
The overvoltage protection module consists of two pins.
The first, OVSENS, is used to measure the externally ap-
plied voltage through an external resistor. The second,
OVGATE, is an output used to drive the gate pin of the
external MOSFET. When OVSENS is below 6V, an internal
charge pump will drive OVGATE to approximately 1.88 ×
OVSENS. This will enhance the N-channel MOSFET and
provide a low impedance connection to V_BUS or WALL
which will, in turn, power the LTC3576/LTC3576-1. If
OVSENS should rise above 6V due to a fault or use of
an incorrect wall adapter, OVGATE will be pulled to GND
disabling the external MOSFET and therefore protecting
downstream circuitry. When the voltage drops below 6V
again, the external MOSFET will be re-enabled.
When USB on-the-go is enabled, the bidirectional switch-
ing regulator powers up the overvoltage protection circuit
through the body diode of the external MOSFET, thus pro-
viding protection to the part even when V_BUS is sourcing
power. When high voltage is applied to the drain of the
external MOSFET, V_BUS will remain at 5V. Once the high
voltage is removed, the drain of the external MOSFET
will return to 5V.
The charge pump output on OVGATE has limited output
drive capability. Care must be taken to avoid leakage on
this pin as it may adversely affect operation.
See the Applications Information section for resistor power
dissipation rating calculations, a table of recommended
components, and examples of dual-input and reverse
input protection.
I²C Interface
The LTC3576/LTC3576-1 may receive commands from a
host (master) using the standard 2-wire I²C interface. The
Timing Diagram shows the timing relationship of the sig-
nals on the bus. The two bus lines, SDA and SCL, must be
HIGH when the bus is not in use. External pull-up resistors
or current sources, such as the LTC1694 I²C accelerator,
are required on these lines. The LTC3576/LTC3576-1are
receive-only slave devices. The I²C control signals, SDA
and SCL are scaled internally to the DV_CC supply. DV_CC
should be connected to the same power supply as the
microcontroller generating the I²C signals.
The I²C port has an undervoltage lockout on the DV_CC
pin. When DV_CC is below approximately 1V, the I²C serial
port is cleared and switching regulators 1, 2 and 3 are
set to full scale.
Bus Speed
The I²C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I²C compliant master
device. It also contains input filters designed to suppress
glitches should the bus become corrupted.
Start and Stop Conditions
A bus master signals the beginning of a communication
to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
high to LOW while SCL is HIGH. When the master has
finished communicating with the slave, it issues a STOP
condition by transitioning SDA from LOW to HIGH while
SCL is high. The bus is then free for communication with
another I²C device.
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