LTC2372-16_15 Datasheet, PDF (40/50 Pages) Linear Technology – 16-Bit, 500ksps, 8-Channel SAR ADC with 96dB SNR

LTC2372-16
Timing Diagrams
Sleep Mode
The LTC2372-16 automatically naps once a conversion has
completed. Only the ADC core powers down in nap mode.
As a result, the auto nap feature provides limited power
savings. To obtain greater power savings, the LTC2372-16
provides a sleep mode. During sleep mode, the entire part
is powered down except for a small standby current result-
ing in a 300μW power dissipation. To enter sleep mode,
toggle CNV twice with no intervening rising edge on SCK
as shown in Figure 28. The part will enter sleep mode on
the falling edge of BUSY from the last conversion initi-
ated. Once in sleep mode, a rising edge on SCK will wake
the part up. Upon emerging from sleep mode, wait t_WAKE
ms before initiating a conversion to allow the reference
and reference buffer to wake-up and charge the bypass
capacitors at REFIN and REFBUF. The serial data I/O bus
is enabled or disabled by RDL during sleep mode. Sleep
mode does not affect the state of the sequencer memory
or memory pointer.
RDL = DON’T CARE
SDI = DON’T CARE
CNV
BUSY
SCK
t_BUSYLH
CONVERT
t_CNVH
NAP
ACQUIRE
t_ACQ
t_HOLD
t_CONV
RDL = DON’T CARE
SDI = DON’T CARE
CNV
t_CNVH
CONVERT
BUSY
SCK
t_BUSYLH
t_CONV
CONVERT
SLEEP
t_CONV
SLEEP
Figure 28. Sleep Mode Timing Diagram
NAP
t_WAKE
CONVERT
NAP
t_WAKE
CONVERT
237218 F28
40
For more information www.linear.com/LTC2372-16
237216f