LTC2372-16_15 Datasheet, PDF (38/50 Pages) Linear Technology – 16-Bit, 500ksps, 8-Channel SAR ADC with 96dB SNR

LTC2372-16
Timing Diagrams
Single Device, Sequencer Programmed
Figure 26 shows the timing for a single device being
operated with RDL and RESET tied to ground. With
RDL grounded, the serial data I/O bus is enabled and
the MSB(D15) of the new conversion data is available
t_DSDOBUSYL after the falling edge of BUSY. The start-of-
sequence (SOS) bit followed by the configuration used
for the conversion just performed is shifted out after the
new conversion data.
When SDI is high at the first rising edge of SCK after
the falling edge of BUSY as shown, the sequencer pro-
gramming window stays open, allowing the sequencer to
be programmed. With the sequencer programming window
open, a valid input configuration is detected on the 8th
rising edge of SCK. At this point, the MUX turns OFF and
resets and sequencer memory is reset and updated with
the new configuration. The new channel configuration is
applied when the MUX turns ON, marking the beginning
of a new acquisition period.
‘On the Fly’ Device Programming
The sequencer may be programmed with one control
word as shown in Figure 26 every conversion cycle to
achieve complete flexibility in the multiplexer configura-
tion, input range and digital gain compression setting on
each conversion.
NAP
RDL = 0
RESET = 0
CNV
BUSY
t_BUSYLH
SCK
CONVERT
t_CNVH
t_HOLD
t_CONV
SDI
SDO
t_DSDOBUSYL
NAP
CONVERT
t_CNVL
t_SCKH
12 34 56 78
t_SSDISCK t_SCKL
t_HSDISCK
C[7] C[6] C[5] C[4] C[3] C[2] C[1] C[0]
t_VLDMRST + t_MRST2 + t_ACQ
t_SCK
9
21 22 23 24
t_HSDO
t_DSDO
t_QUIET
D15 D14 D13 D12 D11 D10 D9 D8 D7
R[1] R[0] SEL
237216 F26
Figure 26. Using a Single LTC2372-16 Programming the Sequencer
38
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