LTC1408-12 Datasheet, PDF (4/20 Pages) Linear Technology – 6 Channel, 12-Bit, 600ksps Simultaneous Sampling ADC with Shutdown

LTC1408-12
POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T_A = 25°C. With internal reference, V_DD = V_CC= 3V.
SYMBOL
V_DD, V_CC
I_DD + I_CC
PARAMETER
Supply Voltage
Supply Current
PD
Power Dissipation
CONDITIONS
Active Mode, f_SAMPLE = 600ksps
Nap Mode
Sleep Mode
Active Mode with SCK, f_SAMPLE = 600ksps
MIN TYP MAX
2.7
3.0
3.6
●
5
7
●
1.1
1.9
2.0
15
15
UNITS
V
mA
mA
µA
mW
WU
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T_A = 25°C. V_DD = 3V.
SYMBOL
f_SAMPLE(MAX)
t_THROUGHPUT
t_SCK
t_CONV
t₁
t₂
t₃
t₄
t₅
t₆
t₇
t₈
t₉
t₁₀
t₁₁
PARAMETER
CONDITIONS
Maximum Sampling Rate per Channel
(Conversion Rate)
Minimum Sampling Period (Conversion + Acquisiton Period)
Clock Period
(Note 16)
Conversion Time
(Notes 6, 17)
Minimum High or Low SCLK Pulse Width
(Note 6)
CONV to SCK Setup Time
(Notes 6, 10)
SCK Before CONV
(Note 6)
Minimum High or Low CONV Pulse Width
(Note 6)
SCK↑ to Sample Mode
(Note 6)
CONV↑ to Hold Mode
(Notes 6, 11)
96th SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13)
Delay from SCK to Valid Bits 0 Through 11
(Notes 6, 12)
SCK↑ to Hi-Z at SDO
(Notes 6, 12)
Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
V_REF Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
MIN
● 100
●
● 100
96
2
3
0
4
4
1.2
45
2
TYP MAX
UNITS
kHz
10
µs
10000
ns
SCLK cycles
ns
10000
ns
ns
ns
ns
ns
ns
8
ns
6
ns
ns
2
ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above V_DD, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V_DD without latchup.
Note 4: Offset and range specifications apply for a single-ended CH0⁺ –
CH5⁺ input with CH0^– – CH5^– grounded and using the internal 2.5V
reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band. Linearity is tested for CH0 only.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between CHx⁺ and CHx^–, x = 0–5.
Note 9: The absolute voltage at CHx⁺ and CHx^– must be within this range.
Note 10: If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
96th rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5V_P-P input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The conversion process takes 16 clocks for each channel that is
enabled, up to 96 clocks for all 6 channels.
140812f
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