LTC1408-12 Datasheet, PDF (1/20 Pages) Linear Technology – 6 Channel, 12-Bit, 600ksps Simultaneous Sampling ADC with Shutdown

FEATURES
■ _{600ksps ADC with 6 Simultaneously Sampled}
Differential Inputs
■ _{100ksps Throughput per Channel}
■ _{72dB SINAD}
■ _{Low Power Dissipation: 15mW}
■ _{3V Single Supply Operation}
■ _{2.5V Internal Bandgap Reference, Can be Overdriven}
with External Reference
■ _{3-Wire SPI-Compatible Serial Interface}
■ _{0V to 2.5V Unipolar, or ±1.25V Bipolar Differential}
Input Range
■ _{SLEEP (6µW) Shutdown Mode}
■ _{NAP (3.3mW) Shutdown Mode}
■ _{Internal Conversion Triggered by CONV}
■ _{83dB Common Mode Rejection}
■ _{Tiny 32-Pin (5mm × 5mm) QFN Package}
U
APPLICATIO S
■ _{Multiphase Power Measurement}
■ _{Multiphase Motor Control}
■ _{Data Acquisition Systems}
■ _{Uninterruptable Power Supplies}
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6084440, 6522187.
LTC1408-12
6 Channel, 12-Bit, 600ksps
Simultaneous Sampling ADC
DESCRIPTIO ^{with Shutdown}
The LTC^®1408-12 is a 12-bit, 600ksps ADC with six
simultaneously sampled differential inputs. The device
draws only 5mA from a single 3V supply, and comes in a
tiny 32 pin (5mm × 5mm) QFN package. A SLEEP shut-
down feature further reduces power consumption to
6µW. The combination of low power and tiny package
makes the LTC1408-12 suitable for portable applications.
The LTC1408-12 contains six separate differential inputs
that are sampled simultaneously on the rising edge of the
CONV signal. These six sampled inputs are then
converted at a rate of 100ksps per channel.
The 83dB common mode rejection allows users to
eliminate ground loops and common mode noise by
measuring signals differentially from the source.
The device converts 0V to 2.5V unipolar inputs differen-
tially, or ±1.25V bipolar inputs also differentially,
depending on the state of the BIP pin. Any analog input
may swing rail-to-rail as long as the differential input
range is maintained.
The conversion sequence can be abbreviated to convert
fewer than six channels, depending on the logic state of
the SEL2, SEL1 and SEL0 inputs.
The serial interface sends out the six conversion results in
96 clocks for compatibility with standard serial interfaces.
BLOCK DIAGRA
CH5^– CH5⁺
CH4^– CH4⁺
CH3^– CH3⁺
CH2^– CH2⁺
CH1^– CH1⁺
CH0^– CH0⁺
21
20 19 18
17 16 15
14 12 11
10
13
–
S AND H
–
S AND H
–
S AND H
–
S AND H
98
7
–
S AND H
65
4
–
S AND H
MUX
2.5V
REFERENCE
10µF
3V
V_CC
V_DD
24
25
600ksps
12-BIT ADC
12-BIT LATCH 0
12-BIT LATCH 1
12-BIT LATCH 2
12-BIT LATCH 3
12-BIT LATCH 4
12-BIT LATCH 5
TIMING
LOGIC
GND
33 22
V_REF
23 29
10µF
BIP
26 27 28
SEL2 SEL1 SEL0
THREE-
STATE
SERIAL
OUTPUT
PORT
3
OV_DD
3V
1 ^SD0
0.1µF
2
OGND
30 CONV
32 SCK
31 DGND
235114 TA01
140812f
1