LTC3862_15 Datasheet, PDF (34/42 Pages) Linear Technology – Multi-Phase Current Mode Step-Up DC/DC Controller

LTC3862
Applications Information
SW1
50V/DIV
I_L1
5A/DIV
SW2
50V/DIV
I_L2
5A/DIV
V_OUT
100mV/DIV
AC COUPLED
V_IN = 24V
V_OUT = 48V, 1.5A
2.5µs/DIV
3862 F27
Figure 27. LTC3862 Switching Waveforms for Boost Converter
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the converter:
1. For lower power applications a 2-layer PC board
is sufficient. However, for higher power levels, a
multilayer PC board is recommended. Using a solid
ground plane and proper component placement under
the circuit is the easiest way to ensure that switching
noise does not affect the operation.
2. In order to help dissipate the power from the MOS-
FETs and diodes, keep the ground plane on the layers
closest to the power components. Use power planes
for the MOSFETs and diodes in order to maximize the
heat spreading from these components into the PCB.
3. Place all power components in a tight area. This will
minimize the size of high current loops. The high di/
dt loops formed by the sense resistor, power MOSFET,
the boost diode and the output capacitor should be
kept as small as possible to avoid EMI.
4. Orient the input and output capacitors and current
sense resistors in a way that minimizes the distance
between the pads connected to the ground plane.
Keep the capacitors for INTV_CC, 3V8 and V_IN as close
as possible to LTC3862.
5. Place the INTV_CC decoupling capacitor as close as
possible to the INTV_CC and PGND pins, on the same
layer as the IC. A low ESR (X5R or better) 4.7μF to
10μF ceramic capacitor should be used.
6. Use a local via to ground plane for all pads that
connect to the ground. Use multiple vias for power
components.
7. Place the small-signal components away from high
frequency switching nodes on the board. The pinout
of the LTC3862 was carefully designed in order to
make component placement easy. All of the power
components can be placed on one side of the IC, away
from all of the small-signal components.
8. The exposed area on the bottom of the QFN package
is internally connected to PGND; however it should
not be used as the main path for high current flow.
9. The MOSFETs should also be placed on the same
layer of the board as the sense resistors. The MOSFET
source should connect to the sense resistor using a
short, wide PCB trace.
10. The output resistor divider should be located as
close as possible to the IC, with the bottom resistor
connected between FB and SGND. The PCB trace
connecting the top resistor to the upper terminal of
the output capacitor should avoid any high frequency
switching nodes.
11. Since the inductor acts like a current source in a peak
current mode control topology, its placement on the
board is less critical than the high di/dt components.
12. The SENSE⁺ and SENSE^– PCB traces should be
routed parallel to one another with minimum spacing
in between all the way to the sense resistor. These
traces should avoid any high frequency switching
nodes in the layout. These PCB traces should also be
Kelvin-connected to the interior of the sense resistor
pads, in order to avoid sensing errors due to parasitic
PCB resistance IR drops.
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