LTC3554-3_15 Datasheet, PDF (31/36 Pages) Linear Technology – Micropower USB Power Manager with Li-Ion Charger and Two Step-Down Regulators

LTC3554/LTC3554-1/
LTC3554-2/LTC3554-3
OPERATION
Holding ON low through the one second power-down
period will not cause a power-up event at end of the one
second period. ON must be brought high following the
power-down event and then go low again for 400ms to
establish a valid power-up event, as shown in Figure 12.
1
BAT
0
1
V_BUS
0
1
ON (PB)
0
1
PBSTAT
0
t_{ON_HR}
50ms
1
BUCK1
0
1
BUCK2
0
1
PWR_ON1
0
1
PWR_ON2
0
1
PGOOD
0
STATE
PON
1s
PDN1
400ms
HR
PUP1
3554 TD06
Figure 12. Hard Reset Via Holding ON Low
Power-Up Sequencing (Except LTC3554-3)
Figure 13 shows the actual power-up sequencing of the
LTC3554. Buck1 and buck2 are both initially disabled (0V).
Once the pushbutton has been applied (ON low) for 400ms
buck1 is enabled. Buck1 slews up and enters regulation.
The actual slew rate is controlled by the soft start function
of buck1 in conjunction with output capacitance and load
(see the Step-Down Switching Regulator Operation sec-
tion for more information). When buck1 is within about
8% of final regulation, buck2 is enabled and slews up
into regulation. 230ms after buck2 is within 8% of final
regulation, the PGOOD output will go high impedance.
The regulators in Figure 13 are slewing up with nominal
output capacitors and no-load. Adding a load or increasing
output capacitance on any of the outputs will reduce the
slew rate and lengthen the time it takes the regulator to
get into regulation. In the LTC3554-3, buck1 and buck2
power up at the same time without sequencing.
V_OUT1
1V/DIV
0V
V_OUT2
0.5V/DIV
0V
100µs/DIV
3554 F13
Figure 13. Power-Up Sequencing
LAYOUT AND THERMAL CONSIDERATIONS
Printed Circuit Board Power Dissipation
In order to be able to deliver maximum charge current
under all conditions, it is critical that the Exposed Pad
on the backside of the LTC3554 package is soldered to
a ground plane on the board. Correctly soldered to a
2500mm² ground plane on a double-sided 1oz copper
board, the LTC3554 has a thermal resistance (q_JA) of ap-
proximately 70°C/W. Failure to make good thermal contact
between the Exposed Pad on the backside of the package
and an adequately sized ground plane will result in thermal
resistances far greater than 70°C/W.
The conditions that cause the LTC3554 to reduce charge
current due to the thermal protection feedback can be
approximated by considering the power dissipated in the
part. For high charge currents the LTC3554 power dis-
sipation is approximately:
P_D = (V_BUS–BAT) • I_BAT + P_D(REGS)
where P_D is the total power dissipated, V_BUS is the supply
voltage, BAT is the battery voltage, and I_BAT is the battery
charge current. P_D(REGS) is the sum of power dissipated
on chip by the step-down switching regulators.
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