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LTC3813 Datasheet, PDF (30/32 Pages) Linear Technology – 100V Current Mode Synchronous Step-Up Controller
LTC3813
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out a PC board follow one of two suggested
approaches. The simple PC board layout requires a dedi-
cated ground plane layer. Also, for higher currents, it is
recommended to use a multilayer board to help with heat
sinking power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
• Place CIN, COUT, MOSFETs, D1 and inductor all in one
compact area. It may help to have some components
on the bottom side of the board.
• Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3813.
Use several bigger vias for power components.
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
• Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low.
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
component. You can connect the copper areas to any
DC net (VIN, VOUT, GND or to any other DC rail in your
system).
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to
the source of M2.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
• Connect the input capacitor(s) CIN close to the pow-
er MOSFETs. This capacitor carries the MOSFET AC
current.
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC and SGND pins.
• Connect the top driver boost capacitor CB closely to
the BOOST and SW pins.
• Connect the bottom driver decoupling capacitor CDRVCC
closely to the DRVCC and BGRTN pins.
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