LTC3813 Datasheet, PDF (26/32 Pages) Linear Technology – 100V Current Mode Synchronous Step-Up Controller

LTC3813
APPLICATIONS INFORMATION
self-consistency between the assumed MOSFET junction
temperature and the resulting value of I_LIMIT which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the R_DS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET
on-resistance. Data sheets typically specify nominal
and maximum values for R_DS(ON), but not a minimum.
A reasonable assumption is that the minimum R_DS(ON)
lies the same percentage below the typical value as the
maximum lies above it. Consult the MOSFET manufacturer
for further guidelines.
Note that in a boost mode architecture, it is only possible
to provide protection for “soft” shorts where V_OUT > V_IN.
For hard shorts, the inductor current is limited only by the
input supply capability.
Soft-Start
The LTC3813 has the ability to soft-start with a capacitor
connected to the SS pin. The LTC3813 is put in a low
quiescent current shutdown state (I_Q ~240μA) if the
SHDN pin voltage is below 1.5V. The SS pin is actively
pulled to ground in this shutdown state. Once the SHDN
pin voltage is above 1.5V, the LTC3813 is powered up. A
soft-start current of 1.4μA then starts to charge the soft-
start capacitor C_SS. Soft-start is achieved by limiting the
maximum output current of the controller by controlling
the ramp rate of the I_TH voltage. The total soft-start time
can be calculated as:
t_SOFTSTART

2.4
•
C_SS
1.4μA
Phase-Locked Loop and Frequency Synchronization
The LTC3813 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range
of the voltage controlled oscillator is ±30% around the
center frequency f_O. The center frequency is the operating
frequency discussed in the Operating Frequency section.
The LTC3813 incorporates a pulse detection circuit that
will detect a clock on the SYNC pin. In turn, it will turn on
the phase-locked loop function. The pulse width of the
clock has to be greater than 400ns and the amplitude of
the clock should be greater than 2V.
The internal oscillator locks to the external clock after the
second clock transition is received. If an external clock
transition is not detected for three successive periods, the
internal oscillator will revert to the frequency programmed
by the R_OFF resistor.
During the start-up phase, phase-locked loop function is
disabled. When LTC3813 is not in synchronization mode,
PLL/LPF pin voltage is set to around 1.215V. Frequency
synchronization is accomplished by changing the inter-
nal off-time current according to the voltage on the
PLL/LPF pin.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the ex-
ternal and internal pulses. This type of phase detector will
not lock up on input frequencies close to the harmonics
of the V_CO center frequency. The PLL hold-in range, Δf_H,
is equal to the capture range, Δf_C:
Δf_H = Δf_C = ±0.3 f_O
The output of the phase detector is a complementary pair of
current sources charging or discharging the external filter
network on the PLL/LPF pin. A simplified block diagram
is shown in Figure 13.
R_LP
2.4V
C_LP
PLL/LPF
SYNC
DIGITAL
PHASE/
FREQUENCY
VCO
DETECTOR
3813 F13
Figure 13. Phase-Locked Loop Block Diagram
3813fb
26