LTC2373-16_15 Datasheet, PDF (30/50 Pages) Linear Technology – 16-Bit, 1Msps, 8-Channel SAR ADC with 96dB SNR

LTC2373-16
Applications Information
edge on SCK will wake the part up. Upon emerging from
sleep mode, wait t_WAKE ms before initiating a conversion
to allow the reference and reference buffer to wake-up
and charge the bypass capacitors at REFIN and REFBUF.
(Refer to the Timing Diagrams section for more detailed
timing information about sleep mode.)
DIGITAL INTERFACE
The LTC2373-16 has a serial digital interface. The flexible
OV_DD supply allows the LTC2373-16 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial data I/O bus is enabled when RDL is low. Serial
output data is clocked out on the SDO pin and serial input
configuration data is clocked in at the SDI pin when an
external clock is applied to the SCK pin if the serial data
I/O bus is enabled. Serial output data transitions on rising
edges of SCK and serial input data is latched on rising edges
of SCK. D15 remains valid till the first rising edge of SCK.
After the 16 bits of the conversion result are shifted out, a
start-of-sequence (SOS) bit followed by the 7-bit control
word corresponding to the conversion result is shifted out.
SDO will remain low after 24 SCK rising edges have been
issued. Clocking out the data and configuration informa-
tion after the conversion will yield the best performance.
Table 5 lists the minimum shift clock frequency needed to
achieve 1Msps throughput when shifting out a different
number of bits.
Table 5. Minimum Shift Clock Frequency vs Number of Bits for 1Msps
Conversion Result
NUMBER OF BITS
16
f_SCK(MHz)
37
Conversion Result + SOS Bit
17
39
Conversion Result + SOS Bit +
24
55
Configuration Data
The configuration of the LTC2373-16 is programmed via
a sequencer through the serial interface. The following
sections describe the various ways the LTC2373-16 can be
programmed, the operation of the sequencer and general
use of the LTC2373-16.
Configuring the LTC2373-16
The various modes of operation of the LTC2373-16 are
programmed by seven bits of an 8-bit control word, C[7:0].
The control word is shifted in at SDI on the rising edges
of SCK, MSB first. The control word is defined as follows:
C[7] C[6] C[5] C[4] C[3] C[2] C[1] C[0]
X A[3] A[2] A[1] A[0] R[1] R[0] SEL
The MSB of the control word, C[7], is used during the
programming of the sequencer and does not control
the operating mode or configuration of the MUX or ADC
(see Programming the Sequencer section). Referring to
Table 6, bits A[3:0] (C[6:3]) control the analog input MUX
channel configuration. Bits R[1:0] (C[2:1]) control the
input range configuration of the ADC and the SEL (C[0])
bit enables/disables the digital gain compression feature
(see Using Digital Gain Compression for Single Supply
Operation section).
Table 6. Description of Decoded Configuration Bits
BITS NAME
BEHAVIOR
[A3:A0] MUX Channel
See Table 4
Configuration Bits
[R1:R0] Input Range
Selection Bits
00 – Pseudo-Differential Unipolar Input
(Straight Binary Output Data Format)
01 – Pseudo-Differential Bipolar Input
(Two’s-Complement Output Data
Format)
10 – Fully Differential Input
(Straight Binary Output Data Format)
11 – Fully Differential Input
(Two’s-Complement Output Data
Format)
SEL Digital Gain
0 – Digital Gain Compression Disabled
Compression Bit 1 – Digital Gain Compression Enabled
Note: Digital gain compression feature always disabled for the pseudo-
differential unipolar input range.
Analog Input Multiplexer
The analog input MUX is programmed by the A[3:0]
(C[6:3]) bits of the input control word. Table 7 lists the
MUX configurations for all combinations of the configu-
ration bits. The selected positive (+) channel is output
to MUXOUT⁺ and the selected negative (−) channel is
output to MUXOUT^−. Figure 17 shows an example of the
MUX configuration being updated on successive conver-
sions. Note how the voltages of the selected positive (+)
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