LTC2373-16_15 Datasheet, PDF (18/50 Pages) Linear Technology – 16-Bit, 1Msps, 8-Channel SAR ADC with 96dB SNR

LTC2373-16
Applications Information
ANALOG INPUTS
The LTC2373-16 can be configured to accept one of
three voltage ranges: fully differential (±4.096V), pseudo-
differential unipolar (0V to 4.096V), and pseudo-differential
bipolar (±2.048V). In all three ranges, the ADC samples and
digitizes the voltage difference between the two ADC core
analog input pins (ADCIN⁺ − ADCIN^−), and any unwanted
signal that is common to both inputs is reduced by the
common mode rejection ratio (CMRR) of the ADC. The
MUX outputs the voltages of the selected MUX analog input
channels to MUXOUT^+/–, according to the MUX configu-
ration. MUXOUT^+/– may be wired directly to ADCIN^+/– or
connected through a buffer. Refer to the Configuring the
LTC2373-16 section for details on how to select the analog
input range and MUX channel configuration.
Independent of the selected range or channel configuration,
the MUX analog inputs can be modeled by the equivalent
circuit shown in Figure 4. CHx and CHy are distinct input
pins selected from the CH0 to CH7 MUX analog inputs,
depending on the MUX configuration. Each pin has ESD
protection diodes. The ADC core analog inputs, ADCIN^+/–,
each see a sampling network consisting of approximately
50pF (C_IN) from the sampling CDAC in series with 40Ω
(R_ON) from the on-resistance of the sampling switch.
The MUX is modeled by a 40Ω resistor representing the
MUX switch on-resistance (R_SW) and a capacitance to
ground, C_PAR, at the output summing node of the MUX.
C_PAR is a lumped capacitance on the order of 20pF formed
primarily by pin parasitics and diode junctions. Parasitic
capacitances from the PCB will also contribute to C_PAR.
This capacitance is discharged through a switch to ground
every conversion cycle or when a first new configuration is
programmed to minimize crosstalk due to charge sharing
between channels.
During acquisition, each active MUX analog input sees a
cascade of two first order lowpass filters formed by R_SW,
C_PAR and the ADC sampling network when MUXOUT^+/– is
wired directly to ADCIN^+/–. If a buffer is inserted between
MUXOUT^+/– and ADCIN^+/–, then each active MUX analog
input only sees a first order lowpass filter formed by R_SW
and C_PAR that is loaded with the input impedance of the
buffer.
Both C_IN and C_PAR draw current spikes while being charged
during acquisition. If MUXOUT^+/– is wired directly to
ADCIN^+/–, the current spikes from the charging of both
capacitors are drawn from the active MUX analog inputs.
A buffer inserted between MUXOUT^+/– and ADCIN^+/– will
absorb the current spike from C_IN, leaving the current spike
from C_PAR to be drawn from the active MUX analog inputs.
During conversion and sleep, the MUX analog inputs and
ADC core analog inputs draw only a small leakage current.
V_DD
CH_X
V_DD
CH_Y, COM
V_DD
V_DD
R_SW
40Ω
OR
R_ON
C_IN
50pF
40Ω
MUXOUT⁺
ADCIN⁺
C_PAR
20pF
BIAS
V_DD
V_DD
VOLTAGE
R_SW
40Ω
OR
R_ON
C_IN
50pF
40Ω
MUXOUT^–
ADCIN^–
C_PAR
20pF
MUX
ADC CORE
237316 F04
Figure 4. Equivalent Circuit for the Differential Analog Inputs of the LTC2373-16
18
For more information www.linear.com/LTC2373-16
237316f