LTC3548-1 Datasheet, PDF (3/16 Pages) Linear Technology – Dual Synchronous, Fixed Output 2.25MHz Step-Down DC/DC Regulator

LTC3548-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C. V_IN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
V_IN
V_OUT1
V_OUT2
ΔV_{LINE REG}
ΔV_{LOAD REG}
I_S
f_OSC
I_LIM
R_DS(ON)
Operating Voltage Range
Output Voltage
Output Voltage
Reference Voltage Line Regulation
Output Voltage Load Regulation
Input DC Supply Current
Active Mode
Sleep Mode
Shutdown
Oscillator Frequency
Peak Switch Current Limit Channel 1
Peak Switch Current Limit Channel 2
Top Switch On-Resistance
Bottom Switch On-Resistance
0°C ≤ T_A ≤ 85°C (Note 3)
–40°C ≤ T_A ≤ 85°C (Note 3)
0°C ≤ T_A ≤ 85°C (Note 3)
–40°C ≤ T_A ≤ 85°C (Note 3)
V_IN = 2.5V to 5.5V (Note 3)
(Note 3)
V_OUT1 = 1.5V, V_OUT2 = 1.3V
V_OUT1 = 1.9V, V_OUT2 = 1.65V
RUN = 0V, V_IN = 5.5V
V_OUT1 = 1.8V, V_OUT2 = 1.575V
V_IN = 3V, Duty Cycle <35%
V_IN = 3V, Duty Cycle <35%
(Note 6)
(Note 6)
● 2.5
5.5
V
1.764 1.8 1.836
V
● 1.755 1.8 1.836
V
1.544 1.575 1.607
V
● 1.536 1.575 1.607
V
0.3 0.5
%/V
0.5
%
700 950
μA
40 60
μA
0.1 1
μA
● 1.8 2.25 2.7
MHz
0.95 1.2 1.6
A
0.6
0.7 0.9
A
0.35 0.45
Ω
0.30 0.45
Ω
I_SW(LKG)
V_RUN
Switch Leakage Current
RUN Threshold
V_IN = 5V, V_RUN = 0V, V_OUT1 = V_OUT2 = 0
0.01 1
μA
● 0.3
1 1.5
V
I_RUN
RUN Leakage Current
●
0.01 1
μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3548-1 is guaranteed to meet specified performance
from 0°C to 85°C. Specifications over the – 40°C and 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: The LTC3548-1 is tested in a proprietary test mode that connects
the output of the error amplifier to an outside servo-loop.
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: T_J is calculated from the ambient T_A and power dissipation P_D
according to the following formula: T_J = T_A + (P_D • θ_JA).
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
TYPICAL PERFORMANCE CHARACTERISTICS T_A = 25°C unless otherwise specified.
Burst Mode Operation
SW
5V/DIV
I_L
200mA/DIV
V_OUT1
20mV/DIV
V_IN = 3.6V
2μs/DIV
V_OUT1 = 1.8V
I_LOAD = 60mA
CHANNEL 1; CIRCUIT OF FIGURE 3
Load Step
V_OUT2
200mV/DIV
I_L
200mA/DIV
I_LOAD
40mA TO
400mA
200mA/DIV
3548-1 G01
V_IN = 3.6V
20μs/DIV
V_OUT2 = 1.575V
I_LOAD = 40mA TO 400mA
CHANNEL 2; CIRCUIT OF FIGURE 3
Load Step
V_OUT1
200mV/DIV
I_L
500mA/DIV
I_LOAD
80mA TO
800mA
500mA/DIV
3548-1 G03
V_IN = 3.6V
20μs/DIV
V_OUT1 = 1.8V
I_LOAD = 80mA TO 800mA
CHANNEL 1; CIRCUIT OF FIGURE 3
3548-1 G02
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