LTC3544_15 Datasheet, PDF (3/16 Pages) Linear Technology – Quad Synchronous Step-Down Regulator

LTC3544
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C. V_IN = 3.6V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
I_S
Input DC Bias Current Active Mode
(Four Regulators Enabled)
V_FB = 0.7V, I_LOAD = 0A, 2.25MHz
825 1100
μA
Sleep Mode
(Four Regulators Enabled)
V_FB = 0.9V, I_LOAD = 0A, 2.25MHz
70
80
μA
Shutdown
0.1
2
μA
f_OSC
Oscillator Frequency
V_RUN(HIGH) RUNx Input High Voltage
V_RUN(LOW) RUNx Input Low Voltage
I_SWx
SWx Leakage
I_RUNx
RUN Leakage Current
I_VFBx
V_FBx Leakage Current
t_SS
Soft-Start Period
V_UVLO
Undervoltage Lockout
Individual Regulator Characteristics
V_IN = 3V
V_IN = 2.5V to 5.5V
2.25
MHz
● 1.8
2.7
MHz
● 1.0
V
●
0.3
V
V_RUN = 0V, V_SW = 0V or 5.5V, V_IN = 5.5V
V_IN = 5.5V
●
±0.1
±1
μA
±0.1
±1
μA
80
nA
V_FB = 7.5% to 92.5% Full Scale
650
875 1200
μs
●
1.9
2.25
V
Regulator SW300 – 300mA
I_PK
Peak Switch Current Limit
I_S300
Input DC Bias Current–Reg SW300 Only
Burst Mode Operation (Sleep)
V_FB < V_FBREG, Duty Cycle < 35%
V_FB = 0.9V, I_LOAD = 0A, 2.25MHz
400
600
800
mA
32
μA
R_PFET
R_DS(ON) of P-Channel FET (Note 7)
R_NFET
R_DS(ON) of N-Channel FET (Note 7)
Regulator SW200A – 200mA
I_SW = 100mA
I_SW = –100mA
0.55
Ω
0.50
Ω
I_PK
Peak Switch Current Limit
V_FB < V_FBREG, Duty Cycle < 35%
I_S200
Input DC Bias Current–Reg SW200A Only
V_FB = 0.9V, I_LOAD = 0A, 2.25MHz
Burst Mode Operation (Sleep)
300
400
500
mA
32
μA
R_PFET
R_DS(ON) of P-Channel FET (Note 7)
R_NFET
R_DS(ON) of N-Channel FET (Note 7)
Regulator SW200B – 200mA
I_SW = 100mA
I_SW = –100mA
0.65
Ω
0.60
Ω
I_PK
Peak Switch Current Limit
V_FB < V_FBREG, Duty Cycle < 35%
I_S200
Input DC Bias Current–Reg SW200B Only
V_FB = 0.9V, I_LOAD = 0A, 2.25MHz
Burst Mode Operation (Sleep)
300
400
500
mA
32
μA
R_PFET
R_DS(ON) of P-Channel FET (Note 7)
R_NFET
R_DS(ON) of N-Channel FET (Note 7)
Regulator SW100 – 100mA
I_SW = 100mA
I_SW = –100mA
0.65
Ω
0.60
Ω
I_PK
Peak Switch Current Limit
V_FB < V_FBREG, Duty Cycle < 35%
I_S100
Input DC Bias Current–Reg SW100B Only
V_FB = 0.9V, I_LOAD = 0A, 2.25MHz
Burst Mode Operation (Sleep)
200
300
400
mA
32
μA
R_PFET
R_NFET
R_DS(ON) of P-Channel FET (Note 7)
R_DS(ON) of N-Channel FET (Note 7)
I_SW = 100mA
I_SW = –100mA
0.80
Ω
0.75
Ω
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3544E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
3544fa
3