LTC3544B_15 Datasheet, PDF (3/18 Pages) Linear Technology – Quad Synchronous Step-Down Regulator

LTC3544B
Electrical Characteristics The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C. V_IN = 3.6V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
V_RUN(HIGH) RUNx Input High Voltage
V_RUN(LOW) RUNx Input Low Voltage
I_LSW
SWx Leakage
I_RUN
RUN Leakage Current
I_VFB
V_FBx Leakage Current
t_SS
Soft-Start Period
V_UVLO
Undervoltage Lockout
Individual Regulator Characteristics
l 1.0
V
l
0.3
V
V_RUN = 0V, V_SW = 0V or 5.5V, V_IN = 5.5V
V_IN = 5.5V
l
±0.1
±1
µA
±0.1
±1
µA
80
nA
V_FB = 7.5% to 92.5% Full Scale
650
875 1200
µs
l
1.9
2.25
V
Regulator SW300 – 300mA
I_PK
Peak Switch Current Limit
I_S300
Input DC Bias Current–Reg SW300 Only
Active Mode (Pulse Skip)
V_FB < V_FBREG, Duty Cycle < 35%
V_FB = 0.7V, I_LOAD = 0A, 2.25MHz
400
600
800
mA
320
µA
R_PFET
R_DS(ON) of P-Channel FET (Note 7)
R_NFET
R_DS(ON) of N-Channel FET (Note 7)
Regulator SW200A – 200mA
I_SW = 100mA
I_SW = –100mA
0.55
Ω
0.50
Ω
I_PK
Peak Switch Current Limit
V_FB < V_FBREG, Duty Cycle < 35%
I_S200
Input DC Bias Current–Reg SW200A Only
V_FB = 0.7V, I_LOAD = 0A, 2.25MHz
Active Mode (Pulse Skip)
300
400
500
mA
320
µA
R_PFET
R_DS(ON) of P-Channel FET (Note 7)
R_NFET
R_DS(ON) of N-Channel FET (Note 7)
Regulator SW200B – 200mA
I_SW = 100mA
I_SW = –100mA
0.65
Ω
0.60
Ω
I_PK
Peak Switch Current Limit
V_FB < V_FBREG, Duty Cycle < 35%
I_S200
Input DC Bias Current–Reg SW200B Only
V_FB = 0.7V, I_LOAD = 0A, 2.25MHz
Active Mode (Pulse Skip)
300
400
500
mA
320
µA
R_PFET
R_DS(ON) of P-Channel FET (Note 7)
R_NFET
R_DS(ON) of N-Channel FET (Note 7)
Regulator SW100 – 100mA
I_SW = 100mA
I_SW = –100mA
0.65
Ω
0.60
Ω
I_PK
Peak Switch Current Limit
V_FB < V_FBREG, Duty Cycle < 35%
I_S100
Input DC Bias Current–Reg SW100B Only
V_FB = 0.7V, I_LOAD = 0A, 2.25MHz
Active Mode (Pulse Skip)
200
300
400
mA
320
µA
R_PFET
R_NFET
R_DS(ON) of P-Channel FET (Note 7)
R_DS(ON) of N-Channel FET (Note 7)
I_SW = 100mA
I_SW = –100mA
0.80
Ω
0.75
Ω
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3544BE is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: T_J is calculated from the ambient temperature T_A and power
dissipation P_D according to the following formula:
T_J = T_A + (P_D)(68°C/W).
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5: The LTC3544B is tested in a proprietary test mode that connects
V_FB to the output of the error amplifier.
Note 6: Load regulation is inferred by measuring the regulation loop gain.
Note 7: The QFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
Note 8: Guaranteed by long-term current density limitations.
3544bfb