LTC3544B_15 Datasheet, PDF (11/18 Pages) Linear Technology – Quad Synchronous Step-Down Regulator

LTC3544B
Applications information
generally far exceeds the I_RIPPLE(P-P) requirement. The
output ripple ΔV_OUT is determined by:
ΔV_OUT
≅
ΔI_L


ESR
+
8
•
ƒ
1
• C_OUT


where f = operating frequency, C_OUT = output capacitance
and ΔI_L = ripple current in the inductor. For a fixed output
voltage, the output ripple is highest at maximum input
voltage since ΔI_L increases with input voltage.
Using Ceramic Input and Output Capacitors
Higher value, lower cost, ceramic capacitors are now
widely available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them
ideal for switching regulator applications. Because the
LTC3544B’s control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size.
However, care must be taken when ceramic capacitors are
used at the input and the output. When a ceramic capacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
induce ringing at the input, V_IN. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, a sudden inrush of current through the long wires
can potentially cause a voltage spike at V_IN, large enough
to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
Output Voltage Programming
The output voltage is set by tying V_FB to a resistive divider
according to the following formula:
V_OUT
=
0.8V


1+
R2 
R1
The external resistive divider is connected to the output
allowing remote voltage sensing as shown in Figure 2.
0.8V ≤ V_OUT ≤ 5.5V
R2
C_F
V_FB
LTC3544B
R1
GND
3544B F02
Figure 2. Setting the LTC3544B Output Voltage
Keeping the current in the resistors small maximizes the
efficiency, but making them too small may allow stray
capacitance to cause noise problems or reduce the phase
margin of the control loop. It is recommended that the
total feedback resistor string be kept to under 100k.
To improve the frequency response of the control loop, a
feed forward capacitor, C_F, may be used. Great care should
be taken to route the feedback line away from noise sources
such as the inductor of the SW line.
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc.
are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3544B circuits: V_IN quiescent current and I²R
losses. V_IN quiescent current loss dominates the efficiency
loss at low load currents, whereas the I²R loss dominates
the efficiency loss at medium to high load currents.
1. The quiescent current is due to two components: the
DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge, dQ, moves
from PV_IN to ground. The resulting dQ/dt is the current out
of PV_IN that is typically larger than the DC bias current and
3544bfb
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