LTC2268-12_15 Datasheet, PDF (3/32 Pages) Linear Technology – 12-Bit, 125Msps/105Msps/ 80Msps Low Power Dual ADCs

LTC2268-12/
LTC2267-12/LTC2266-12
converter Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C. (Note 5)
LTC2268-12
LTC2267-12
LTC2266-12
PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Resolution
(No Missing Codes)
l 12
12
12
Bits
Integral Linearity Error
Differential Analog Input
(Note 6)
l –1 ±0.3 1 –1 ±0.3 1 –1 ±0.3 1
LSB
Differential Linearity Error Differential Analog Input
l –0.5 ±0.1 0.5 –0.4 ±0.1 0.4 –0.4 ±0.1 0.4
LSB
Offset Error
(Note 7)
l –12 ±3 12 –12 ±3 12 –12 ±3 12
mV
Gain Error
Internal Reference
External Reference
–0.9
–0.9
–0.9
%FS
l –2.4 –0.9 0.6 –2.4 –0.9 0.6 –2.4 –0.9 0.6
%FS
Offset Drift
±20
±20
±20
µV/°C
Full-Scale Drift
Internal Reference
External Reference
±30
±30
±30
ppm/°C
±10
±10
±10
ppm/°C
Gain Matching
External Reference
±0.2
±0.2
±0.2
%FS
Offset Matching
±3
±3
±3
mV
Transition Noise
External Reference
0.3
0.3
0.3
LSB_RMS
analog input The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T_A = 25°C. (Note 5)
SYMBOL PARAMETER
V_IN
Analog Input Range (A_IN+ – A_IN–)
V_IN(CM) Analog Input Common Mode (A_IN+ – A_IN–)/2
V_SENSE External Voltage Reference Applied to SENSE
I_INCM Analog Input Common Mode Current
I_IN1
I_IN2
I_IN3
t_AP
t_JITTER
CMRR
Analog Input Leakage Current (No Encode)
PAR/SER Input Leakage Current
SENSE Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
CONDITIONS
1.7V < V_DD < 1.9V
Differential Analog Input (Note 8)
External Reference Mode
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
0 < A_IN+, A_IN– < V_DD
0 < PAR/SER < V_DD
0.625 < SENSE < 1.3V
MIN
l
l V_CM – 100mV
l
0.625
l
l
–1
l
–3
l
–6
TYP
1 to 2
V_CM
1.25
155
130
100
0
0.15
80
MAX
V_CM +100mV
1.3
1
3
6
UNITS
V_P–P
V
V
µA
µA
µA
µA
µA
µA
ns
ps_RMS
dB
BW-3B Full Power Bandwidth
Figure 6 Test Circuit
800
MHz
22687612fa
3