LTC2268-12_15 Datasheet, PDF (1/32 Pages) Linear Technology – 12-Bit, 125Msps/105Msps/ 80Msps Low Power Dual ADCs

LTC2268-12/
LTC2267-12/LTC2266-12
12-Bit, 125Msps/105Msps/
80Msps Low Power Dual ADCs
Features
n _{2-Channel Simultaneous Sampling ADC}
n _{70.6dB SNR}
n _{88dB SFDR}
n _{Low Power: 292mW/238mW/200mW Total,}
146mW/119mW/100mW per Channel
n _{Single 1.8V Supply}
n _{Serial LVDS Outputs: 1 or 2 Bits per Channel}
n _{Selectable Input Ranges: 1VP-P to 2VP-P}
n _{800MHz Full Power Bandwidth S/H}
n _{Shutdown and Nap Modes}
n _{Serial SPI Port for Configuration}
n _{Pin Compatible 14-Bit and 12-Bit Versions}
n _{40-Pin (6mm × 6mm) QFN Package}
Applications
n _{Communications}
n _{Cellular Base Stations}
n _{Software Defined Radios}
n _{Portable Medical Imaging}
n _{Multichannel Data Acquisition}
n _{Nondestructive Testing}
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Description
The LTC^®2268-12/LTC2267-12/LTC2266-12 are 2-channel,
simultaneous sampling 12-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 70.6dB SNR and
88dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.15ps_RMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.3LSB_RMS.
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode). The LVDS drivers have
optional internal termination and adjustable output levels
to ensure clean signal integrity.
The ENC⁺ and ENC^– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
Typical Application
1.8V
V_DD
1.8V
OV_DD
CH.1
ANALOG
S/H
INPUT
12-BIT
ADC CORE
OUT1A
OUT1B
CH.2
ANALOG
S/H
INPUT
ENCODE
INPUT
12-BIT
ADC CORE
PLL
DATA
SERIALIZER
OUT2A
OUT2B
DATA
CLOCK
OUT
FRAME
GND
OGND
226812 TA01
SERIALIZED
LVDS
OUTPUTS
LTC2268-12, 125Msps,
2-Tone FFT, f_IN = 70MHz and 75MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 10 20 30 40 50 60
FREQUENCY (MHz)
226812 TA01b
22687612fa
1