LTM9011-14_15 Datasheet, PDF(28/40 Page) Linear Technology – 14-Bit, 125Msps/105Msps/ 80Msps Low Power Octal ADCs

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LTM9011-14_15 Datasheet, PDF (28/40 Pages) Linear Technology – 14-Bit, 125Msps/105Msps/ 80Msps Low Power Octal ADCs

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LTM9011-14/

LTM9010-14/LTM9009-14

APPLICATIONS INFORMATION

Digital Output Test Pattern

To allow in-circuit testing of the digital interface to the

A/D, there is a test mode that forces the A/D data outputs

(D13-D0) of all channels to known values. The digital

output test patterns are enabled by serially programming

mode control registers A3 and A4. When enabled, the test

patterns override all other formatting modes: 2âs comple-

ment and randomizer.

Output Disable

The digital outputs may be disabled by serially program-

ming mode control register A2. The current drive for all

digital outputs including DCO and FR are disabled to save

power or enable in-circuit testing. When disabled the com-

mon mode of each output pair becomes high impedance,

but the differential impedance may remain low.

DEVICE PROGRAMMING MODES

The operating modes of the LTM9011-14/LTM9010-14/

LTM9009-14 can be programmed by either a parallel

interface or a simple serial interface. The serial interface

has more flexibility and can program all available modes.

The parallel interface is more limited and can only program

some of the more commonly used modes.

Parallel Programming Mode

To use the parallel programming mode, PAR/SER should

be tied to VDD. The CS, SCK, SDI and SDO pins are binary

logic inputs that set certain operating modes. These pins

can be tied to VDD or ground, or driven by 1.8V, 2.5V, or

3.3V CMOS logic. When used as an input, SDO should

be driven through a 1k series resistor. Table 3 shows the

modes set by CS, SCK, SDI and SDO.

Sleep and Nap Modes

The A/D may be placed in sleep or nap modes to conserve

power. In sleep mode the entire device is powered down,

resulting in 2mW power consumption. Sleep mode is

enabled by mode control register A1 (serial programming

mode), or by SDI (parallel programming mode). The time

required to recover from sleep mode is about 2ms.

In nap mode any combination of A/D channels can be

powered down while the internal reference circuits and the

PLL stay active, allowing faster wakeup than from sleep

mode. Recovering from nap mode requires at least 100

clock cycles. If the application demands very accurate DC

settling then an additional 50Âµs should be allowed so the

on-chip references can settle from the slight temperature

shift caused by the change in supply current as the A/D

leaves nap mode. Nap mode is enabled by mode control

Table 3. Parallel Programming Mode Control Bits

(PAR/SER = VDD)

DESCRIPTION

2-Lane / 1-Lane Selection Bit

0 = 2-Lane, 16-Bit Serialization Output Mode

1 = 1-Lane, 14-Bit Serialization Output Mode

SCK

LVDS Current Selection Bit

0 = 3.5mA LVDS Current Mode

1 = 1.75mA LVDS Current Mode

SDI

Power Down Control Bit

0 = Normal Operation

1 = Sleep Mode

SDO

Internal Termination Selection Bit

0 = Internal Termination Disabled

1 = Internal Termination Enabled

Serial Programming Mode

To use the serial programming mode, PAR/SER should be

tied to ground. The CS, SCK, SDI and SDO pins become a

serial interface that program the A/D mode control registers.

Data is written to a register with a 16-bit serial word. Data

can also be read back from a register to verify its contents.

Serial data transfer starts when CS is taken low. The

data on the SDI pin is latched at the first 16 rising

edges of SCK. Any SCK rising edges after the first 16

For more information www.linear.com/LTM9011-14

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