LTC3850-2_15 Datasheet, PDF (27/36 Pages) Linear Technology – Dual, 2-Phase Synchronous Step-Down Switching Controller

LTC3850-2
APPLICATIONS INFORMATION
2.2Ω
1μF
22μF
50V
V_IN
7V TO
20V
V_OUT1
3.3V
5A
L1
3.3μH
6.19k
1%
33pF
4.7μF
M1
0.1μF
1.33k
1%
0.1μF
D3 _{VIN PGOOD EXTVCC INTVCC}
TG1
TG2
BOOST1
BOOST2
SW1
SW2
BG1
LTC3850-2
BG2
MODE/PLLIN
PGND
FREQ/PLLFLTR
SENSE1⁺
SENSE2⁺
SENSE1^–
RUN1
SENSE2^–
RUN2
D4
0.1μF
10k, 1%
0.1μF
M2
L2
2.2μH
4.12k
1%
1.5k
1%
33pF
63.4k
1%
C_OUT1
20k
100μF
1%
X2
1800pF
4.75k
1%
V_FB1
I_TH1
100pF ^TK/SS1
0.1μF
L1, L2: COILTRONICS HCP0703
M1, M2: VISHAY SILICONIX Si4816BDY
C_OUT1, C_OUT2: TAIYO YUDEN JMK325BJ107MM
SGND
V_FB2
I_TH2
TK/SS2
0.1μF
3.16k
1%
2200pF
5.49k
1%
100pF
25.5k
1%
20k
1%
38502 F14
Figure 14. High Efficiency Dual 500kHz 3.3V/1.8V Step-Down Converter
V_OUT2
1.8V
5A
C_OUT2
100μF
X2
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can suggest
noise pickup at the current or voltage sensing inputs or
inadequate loop compensation. Overcompensation of the
loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controller is checked for its individual performance should
both controllers be turned on at the same time. A particularly
difficult region of operation is when one controller channel
is nearing its current comparator trip point when the other
channel is turning on its top MOSFET. This occurs around
50% duty cycle on either channel due to the phasing of the
internal clocks and may cause minor duty cycle jitter.
Reduce V_IN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering V_IN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between C_IN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
38502f
27