LTC2260-14_15 Datasheet, PDF (27/34 Pages) Linear Technology – 14-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs

LTC2261-14
LTC2260-14/LTC2259-14
Applications Information
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
X
X
X
X
CLKINV
CLKPHASE1
CLKPHASE0
Bits 7-4
Unused, Don’t Care Bits.
Bit 3
CLKINV Output Clock Invert Bit
0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits
00 = No CLKOUT Delay (As Shown in the Timing Diagrams)
01 = CLKOUT⁺/CLKOUT^– Delayed by 45° (Clock Period • 1/8)
10 = CLKOUT⁺/CLKOUT^– Delayed by 90° (Clock Period • 1/4)
11 = CLKOUT⁺/CLKOUT^– Delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT Phase Delay Feature is Used, the Clock Duty Cycle Stabilizer Must Also be Turned On
Bit 0
DCS Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7
D6
D5
D4
D3
D2
D1
X
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTMODE1
Bit 7
Unused, Don’t Care Bit.
Bits 6-4
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 3
TERMON LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 1.6× the Current Set by ILVDS2:ILVDS0
Bit 2
OUTOFF
Output Disable Bit
0 = Digital Outputs are Enabled
1 = Digital Outputs are Disabled and Have High Output Impedance
Bits 1-0
OUTMODE1:OUTMODE0 Digital Output Mode Control Bits
00 = Full-Rate CMOS Output Mode
01 = Double-Data Rate LVDS Output Mode
10 = Double-Data Rate CMOS Output Mode
11 = Not Used
D0
DCS
D0
OUTMODE0
For more information www.linear.com/LTC2261-14
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