LTC2260-14_15 Datasheet, PDF (1/34 Pages) Linear Technology – 14-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs

Features
n _{73.4dB SNR}
n _{85dB SFDR}
n _{Low Power: 127mW/106mW/89mW}
n _{Single 1.8V Supply}
n _{CMOS, DDR CMOS or DDR LVDS Outputs}
n _{Selectable Input Ranges: 1VP-P to 2VP-P}
n _{800MHz Full-Power Bandwidth S/H}
n _{Optional Data Output Randomizer}
n _{Optional Clock Duty Cycle Stabilizer}
n _{Shutdown and Nap Modes}
n _{Serial SPI Port for Configuration}
n _{Pin Compatible 14-Bit and 12-Bit Versions}
n _{40-Pin (6mm × 6mm) QFN Package}
Applications
n _{Communications}
n _{Cellular Base Stations}
n _{Software Defined Radios}
n _{Portable Medical Imaging}
n _{Multi-Channel Data Acquisition}
n _{Nondestructive Testing}
LTC2261-14
LTC2260-14/LTC2259-14
14-Bit, 125/105/80Msps
Ultralow Power 1.8V ADCs
Description
The LTC^®2261-14/LTC2260-14/LTC2259-14 are sam-
pling 14-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. They are perfect
for demanding communications applications with AC
performance that includes 73.4dB SNR and 85dB spurious
free dynamic range (SFDR). Ultralow jitter of 0.17ps_RMS
allows undersampling of IF frequencies with excellent
noise performance.
DC specs include ±1LSB INL (typical), ±0.3LSB DNL (typi-
cal) and no missing codes over temperature. The transition
noise is a low 1.2LSB_RMS.
The digital outputs can be either full-rate CMOS, double-
data rate CMOS, or double-data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC⁺ and ENC^– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
ANALOG
INPUT
+
INPUT
S/H
–
1.8V
V_DD
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
CLOCK/DUTY
CYCLE
CONTROL
GND
125MHz
CLOCK
OUTPUT
DRIVERS
1.2V
TO 1.8V
OV_DD
D13
• CMOS
• OR
• LVDS
D0
OGND
226114 TA01a
2-Tone FFT, f_IN = 70MHz and 75MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 10 20 30 40 50 60
FREQUENCY (MHz)
226114 TA01b
For more information www.linear.com/LTC2261-14
226114fc
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