LTC3731H Datasheet, PDF (26/32 Pages) Linear Technology – 3-Phase, 600kHz, Synchronous Buck Switching Regulator Controller

LTC3731H
APPLICATIO S I FOR ATIO
The worst-case input RMS ripple current for a single stage
design peaks at twice the value of the output voltage. The
worst-case input RMS ripple current for a two stage
design results in peaks at 1/4 and 3/4 of the input voltage,
and the worst-case input RMS ripple current for a three
stage design results in peaks at 1/6, 1/2, and 5/6 of the
input voltage. The peaks, however, are at ever decreasing
levels with the addition of more phases. A higher effective
duty factor results because the duty factors “add” as long
as the currents in each stage are balanced. Refer to AN19
for a detailed description of how to calculate RMS current
for the single stage switching regulator.
Figure 6 illustrates the RMS input current drawn from the
input capacitance versus the duty cycle as determined by
the ration of input and output voltage. The peak input RMS
current level of the single phase system is reduced by 2/3
in a 3-phase solution due to the current splitting between
the three stages.
The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the V_OUT/L discharge currents
term from the stages that has their bottom MOSFETs on
subtract current from the (V_CC – V_OUT)/L charging current
resulting from the stage which has its top MOSFET on. The
output ripple current for a 3-phase design is:
I_P-P
=
V_OUT
(^f)(^L)
(^1–
3DC₎
V_IN > 3V_OUT
The ripple frequency is also increased by three, further
reducing the required output capacitance when V_CC < 3V_OUT
as illustrated in Figure 6.
The addition of more phases by phase locking additional
controllers, always results in no net input or output ripple
at V_OUT/V_IN ratios equal to the number of stages
implemented. Designing a system with multiple stages
close to the V_OUT/V_IN ratio will significantly reduce the
ripple voltage at the input and outputs and thereby
improve efficiency, physical size and heat generation of
the overall switching power supply. Refer to Application
Note 77 for more information on Polyphase circuits.
26
Efficiency Calculation
To estimate efficiency, the DC loss terms include the input
and output capacitor ESR, each MOSFET R_DS(ON), induc-
tor resistance R_L, the sense resistance R_SENSE and the
forward drop of the Schottky rectifier at the operating
output current and temperature. Typical values for the
design example given previously in this data sheet are:
Main MOSFET R_DS(ON) = 7mΩ (9mΩ at 90°C)
Sync MOSFET R_DS(ON) = 7mΩ (9mΩ at 90°C)
C_INESR = 20mΩ
C_OUTESR = 3mΩ
R_L = 2.5mΩ
R_SENSE = 3mΩ
V_SCHOTTKY = 0.8V at 15A (0.7V at 90°C)
V_OUT = 1.3V
V_IN = 12V
I_MAX = 45A
δ = 0.5%°C (MOSFET temperature coefficient)
N=3
f = 400kHz
The main MOSFET is on for the duty factor V_OUT/ V_IN and
the synchronous MOSFET is on for the rest of the period
or simply (1 – V_OUT/V_IN). Assuming the ripple current is
small, the AC loss in the inductor can be made small if a
good quality inductor is chosen. The average current,
I_OUT is used to simplify the calaculations. The equation
below is not exact but should provide a good technique
for the comparison of selected components and give a
result that is within 10% to 20% of the final application.
The temperature of the MOSFET’s die temperature may
require interative calculations if one is not familiar typical
performance. A maximum operating junction tempera-
ture of 90° to 100°C for the MOSFETs is recommended
for high reliability applications.
Common output path DC loss:
( ) ^P_COMPATH
≈
N^{⎛⎝⎜}
I_MAX
N
⎞
⎠⎟
2
R_L + R_SENSE
+ C_OUTESR Loss
This totals 3.7W + C_OUTESR loss.
3731hf