LTC3557 Datasheet, PDF (26/28 Pages) Linear Technology – USB Power Manager with Li-Ion Charger and Three Step-Down Regulators

LTC3557/LTC3557-1
APPLICATIONS INFORMATION
If an external buck switching regulator controlled by the
LTC3557/LTC3557-1 V_C pin is used instead of a 5V wall
adapter we see a significant reduction in power dissipated
by the LTC3557/LTC3557-1. This is because the external
buck switching regulator will drive the PowerPath output
(V_OUT) to about 3.6V with the battery at 3.3V. If you go
through the example above and substitute 3.6V for V_OUT
we see that thermal regulation does not kick in until about
93°C. Thus, the external regulator not only allows higher
charging currents, but lower power dissipation means a
cooler running application.
Printed Circuit Board Layout Considerations
When laying out the printed circuit board, the following
list should be followed to ensure proper operation of the
LTC3557/LTC3557-1:
1. The Exposed Pad of the package (Pin 29) should connect
directly to a large ground plane to minimize thermal and
electrical impedance.
2. The trace connecting the step-down switching regulator
input supply pins (V_IN1 and V_IN2) and their respective
decoupling capacitors should be kept as short as
possible. The GND side of these capacitors should
connect directly to the ground plane of the part. These
capacitors provide the AC current to the internal power
MOSFETs and their drivers. It’s important to minimize
inductance from these capacitors to the pins of the
LTC3557/LTC3557-1. Connect V_IN1 and V_IN2 to V_OUT
through a short low impedance trace.
3. The switching power traces connecting SW1, SW2 and
SW3 to their respective inductors should be minimized
to reduce radiated EMI and parasitic coupling. Due to
the large voltage swing of the switching nodes, sensitive
nodes such as the feedback nodes (FB1, FB2 and FB3)
should be kept far away or shielded from the switching
nodes or poor performance could result.
4. Connections between the step-down switching regulator
inductors and their respective output capacitors should
be kept as short as possible. The GND side of the output
capacitors should connect directly to the thermal ground
plane of the part.
5. Keep the feedback pin traces (FB1, FB2 and FB3) as
short as possible. Minimize any parasitic capacitance
between the feedback traces and any switching node
(i.e., SW1, SW2, SW3 and logic signals). If necessary
shield the feedback nodes with a GND trace
6) Connections between the LTC3557/LTC3557-1
power path pins (V_BUS and V_OUT) and their respective
decoupling capacitors should be kept as short as pos-
sible. The GND side of these capacitors should connect
directly to the ground plane of the part. V_OUT should be
decoupled with a 10μF or greater ceramic capacitor as
close as possible to the LTC3557/LTC3557-1.
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