LTC3554-2_15 Datasheet, PDF (26/36 Pages) Linear Technology – Micropower USB Power Manager with Li-Ion Charger and Two Step-Down Regulators

LTC3554/LTC3554-1/
LTC3554-2/LTC3554-3
OPERATION
In the HR state, all supplies are disabled. The PowerPath
circuitry is placed in an ultralow quiescent state to minimize
battery drain. If no external charging supply is present
(V_BUS) then the ideal diode is shut down, disconnecting
V_OUT from BAT to further minimize battery drain. The ultra-
low power consumption in the HR state makes it ideal for
shipping or long term storage, minimizing battery drain.
The following events cause the state machine to transition
out of HR into the power-up (PUP1) state:
ON input low for 400ms (PB400MS)
Application of external power (EXTPWR)
Upon entering the PUP1 state, the pushbutton circuitry
will sequence up the two step-down switching regula-
tors, buck1 followed by buck2 (except LTC3554-3). In the
LTC3554-3, buck1 and buck2 are simultaneously enabled.
The PWR_ON1 and PWR_ON2 inputs are ignored in the
PUP1 state. The state machine remains in the PUP1 state
for five seconds. During the five seconds, the application’s
microprocessor, powered by the switching regulators, has
time to boot and assert PWR_ON1 and/or PWR_ON2.
Five seconds after entering the PUP1 state, the pushbut-
ton circuitry automatically transitions into the power-on
(PON) state.
In the PON state, the switching regulators can be enabled
and shut down at any time by the PWR_ON1 and PWR_ON2
pins. A high on PWR_ON1 is needed to keep buck1 en-
abled, and a high on PWR_ON2 is needed to keep buck2
enabled. To remain in the PON state, the application circuit
must keep at least one of the PWR_ON inputs high, else
the state machine enters the power-down (PDN2) state.
When PWR_ON1 and PWR_ON2 are both low, or when
V_OUT drops to its undervoltage lockout (V_OUT UVLO)
threshold, the state machine will leave the PON state and
enter the power-down (PDN2) state. In the power-down
state (PDN2), both switching regulators are kept disabled
regardless of the states of the PWR_ON pins. The state
machine remains in the power-down state for one second,
before automatically entering the power-off (POFF) state.
This one second delay allows all LTC3554 generated sup-
plies time to power down completely before they can be
re-enabled.
The same events used to exit the hard reset (HR) state
are also used to exit the POFF state and enter the PUP2
state. The PUP2 state operates in the same manner as the
PUP1 state previously described.
Both bucks remain powered up during the five second
power-up (PUP1 or PUP2) period, regardless of the state
of the PWR_ON inputs.
In either the HR or POFF states, if any PWR_ON pin is
driven high, the pushbutton circuitry directly enters the
PON state, without passing through the power-up (PUP1
or PUP2) states. This is because by asserting logic high
on the PWR_ON1 or PWR_ON2 pins, the application has
already told the LTC3554 exactly which buck(s) to turn
on, so there is no need for an intermediate PUP state in
which both bucks are enabled for five seconds.
Starting from the HR state, bringing any PWR_ON pin high
enables the PowerPath, if it wasn’t already enabled due
to V_BUS power being available. This powers up the V_OUT
pin from V_BUS or BAT. When the V_OUT voltage rises above
the V_OUT UVLO threshold, the state machine transitions
from the HR state into the PON state, allowing the selected
buck(s) to turn on.
The hard reset (HRST) event is generated by pressing
and holding the pushbutton (ON input low) for 5 seconds
for LTC3554/LTC3554-1 (14 seconds for LTC3554-2/
LTC3554‑3). For a valid HRST event to occur the button
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