LTC3780EG Datasheet, PDF (24/30 Pages) Linear Technology – High Efficiency, Synchronous,4-Switch Buck-Boost Controller

LTC3780
APPLICATIONS INFORMATION
Double-check the T_J in the MOSFET with 70°C ambient
temperature:
T_J = 70°C + 1.94W • 40°C/W = 147.6°C
The maximum power dissipation of switch B occurs in
buck mode. Assuming a junction temperature of T_J = 80°C
with ρ_80°C = 1.2, the power dissipation at V_IN = 18V is:
P_B,BUCK
=
18 – 12
18
•
5²
•
1.2
•
0.009
=
90mW
Double-check the T_J in the MOSFET at 70°C ambient
temperature:
T_J = 70°C + 0.09W • 40°C/W = 73.6°C
The maximum power dissipation of switch C occurs in boost
mode. Assuming a junction temperature of T_J = 110°C with
ρ_110°C = 1.4, the power dissipation at V_IN = 5V is:
P_C,BOOST
=
(12– 5)
5²
• 12
•
5²
• 1.4
•
0.009
+
2
•
12³
•
5
5
•
150p
•
400k
=
1.27W
Double-check the T_J in the MOSFET at 70°C ambient
temperature:
T_J = 70°C + 1.08W • 40°C/W = 113°C
The maximum power dissipation of switch D occurs
in boost mode when its duty cycle is higher than 50%.
Assuming a junction temperature of T_J = 100°C with
ρ_100°C = 1.35, the power dissipation at V_IN = 5V is:
P_D,BOOST
=
5
12
•


12
5
•
5_{}
2
•
1.35
•
0.009
=
0.73W
Double-check the T_J in the MOSFET at 70°C ambient
temperature:
T_J = 70°C + 0.73W • 40°C/W = 99°C
C_IN is chosen to filter the square current in buck mode. In
this mode, the maximum input current peak is:
I_{IN,PEAK(MAX,BUCK)}
=
5
•


1+
29%
2


=
5.7A
A low ESR (10mΩ) capacitor is selected. Input voltage
ripple is 57mV (assuming ESR dominate ripple).
C_OUT is chosen to filter the square current in boost mode.
In this mode, the maximum output current peak is:
I_{OUT,PEAK(MAX,BOOST)}
=
12
5
•
5
•


1+
11%
2


=
10.6A
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 53mV (assuming ESR
dominate ripple).
PC Board Layout Checklist
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
• Place C_IN, switch A, switch B and D1 in one com-
pact area. Place C_OUT, switch C, switch D and D2 in
one compact area. One layout example is shown in
Figure 10.
V_IN
QA
C_IN
SW2
SW1
L
D1
QB
QC
V_OUT
D2
QD
C_OUT
R_SENSE
LTC3780
CKT
Figure 10. Switches Layout
GND
3780 F10
3780ff
24
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