LTC3780EG Datasheet, PDF (10/30 Pages) Linear Technology – High Efficiency, Synchronous,4-Switch Buck-Boost Controller

LTC3780
Pin Functions (SSOP/QFN)
PGOOD (Pin 1/Pin 30): Open-Drain Logic Output. PGOOD
is pulled to ground when the output voltage is not within
±7.5% of the regulation point.
SS (Pin 2/Pin 31): Soft-start reduces the input power
sources’ surge currents by gradually increasing the
controller’s current limit. A minimum value of 6.8nF is
recommended on this pin.
SENSE⁺ (Pin 3/Pin 1): The (+) Input to the Current Sense
and Reverse Current Detect Comparators. The I_TH pin volt-
age and built-in offsets between SENSE^– and SENSE⁺ pins,
in conjunction with R_SENSE, set the current trip threshold.
SENSE^– (Pin 4/Pin 2): The (–) Input to the Current Sense
and Reverse Current Detect Comparators.
I_TH (Pin 5/Pin 3): Current Control Threshold and Error
Amplifier Compensation Point. The current comparator
threshold increases with this control voltage. The voltage
ranges from 0V to 2.4V.
V_OSENSE (Pin 6/Pin 4): Error Amplifier Feedback Input.
This pin connects the error amplifier input to an external
resistor divider from V_OUT.
SGND (Pin 7/Pin 5, Exposed Pad Pin 33): Signal Ground. All
small-signal components and compensation components
should connect to this ground, which should be connected
to PGND at a single point. The QFN exposed pad must be
soldered to PCB ground for electrical connection and rated
thermal performance.
RUN (Pin 8/Pin 6): Run Control Input. Forcing the RUN
pin below 1.5V causes the IC to shut down the switching
regulator circuitry. There is a 100k resistor between the
RUN pin and SGND in the IC. Do not apply >6V to this pin.
FCB (Pin 9/Pin 7): Forced Continuous Control Input. The
voltage applied to this pin sets the operating mode of the
controller. When the applied voltage is less than 0.8V, the
forced continuous current mode is active. When this pin
is allowed to float, the Burst Mode operation is active in
boost operation and the skip-cycle mode is active in buck
operation. When the pin is tied to INTV_CC, the constant
frequency discontinuous current mode is active in buck
or boost operation.
PLLFLTR (Pin 10/Pin 8): The phase-locked loop’s
lowpass filter is tied to this pin. Alternatively, this pin can
be driven with an AC or DC voltage source to vary the
frequency of the internal oscillator.
PLLIN (Pin 11/Pin 10): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
with 50kΩ. The phase-locked loop will force the rising
bottom gate signal of the controller to be synchronized
with the rising edge of the PLLIN signal.
STBYMD (Pin 12/Pin 11): LDO Control Pin. Determines
whether the internal LDO remains active when the control-
ler is shut down. See Operation section for details. If the
STBYMD pin is pulled to ground, the SS pin is internally
pulled to ground, preventing start-up and thereby provid-
ing a single control pin for turning off the controller. To
keep the LDO active when RUN is low, for example to
power a “wake up” circuit which controls the state of the
RUN pin, bypass STBYMD to signal ground with a 0.1µF
capacitor, or use a resistor divider from V_IN to keep the
pin within 2V to 5V.
BOOST2, BOOST1 (Pins 13, 24/Pins 14, 27): Boosted
Floating Driver Supply. The (+) terminal of the bootstrap
capacitor C_A and C_B (Figure 11) connects here. The BOOST2
pin swings from a diode voltage below INTV_CC up to V_IN
+ INTV_CC. The BOOST1 pin swings from a diode voltage
below INTV_CC up to V_OUT + INTV_CC.
TG2, TG1 (Pins 14, 23/Pins 15, 26): Top Gate Drive. Drives
the top N-channel MOSFET with a voltage swing equal to
INTV_CC superimposed on the switch node voltage SW.
SW2, SW1 (Pins 15, 22/Pins 17, 24): Switch Node. The (–)
terminal of the bootstrap capacitor C_A and C_B (Figure 11)
connects here. The SW2 pin swings from a Schottky diode
(external) voltage drop below ground up to V_IN. The SW1
pin swings from a Schottky diode (external) voltage drop
below ground up to V_OUT.
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