LTM9001-AX_15 Datasheet, PDF (23/30 Pages) Linear Technology – 16-Bit IF/Baseband Receiver Subsystem

LTM9001-Ax/LTM9001-Bx
APPLICATIONS INFORMATION
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTM9001 should drive a minimum
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
output may be used but is not required since the ADC has
a series resistor of 43Ω on chip.
Lower OV_DD voltages will also help reduce interference
from the digital outputs.
Digital Output Buffers (LVDS Modes)
Figure 11 shows an equivalent circuit for an LVDS output
pair. A 3.5mA current is steered from OUT⁺ to OUT^– or vice
versa, which creates a ±350mV differential voltage across
the 100Ω termination resistor at the LVDS receiver.
A feedback loop regulates the common mode output volt-
age to 1.2V. For proper operation each LVDS output pair
must be terminated with an external 100Ω termination
resistor, even if the signal is not used (such as OF⁺/OF^– or
CLKOUT⁺/CLKOUT^–). To minimize noise the PC board
traces for each LVDS output pair should be routed close
together. To minimize clock skew all LVDS PC board traces
should have about the same length.
In low power LVDS mode 1.75mA is steered between
the differential outputs, resulting in ±175mV at the LVDS
receiver’s 100Ω termination resistor. The output common
mode voltage is 1.2V, the same as standard LVDS mode.
Data Format
The LTM9001 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MODE pin. This pin has a four level
logic input, centered at 0, 1/3V_DD, 2/3V_DD and V_DD. An
external resistive divider can be used to set the 1/3V_DD
and 2/3V_DD logic levels. Table 5 shows the logic states
for the MODE pin.
Table 5. MODE Pin Function
MODE OUTPUT FORMAT
0V(GND) Offset Binary
1/3V_DD
Offset Binary
2/3V_DD 2’s Complement
V_DD
2’s Complement
CLOCK DUTY CYCLE STABILIZER
Off
On
On
Off
Overflow Bit
An overflow output bit (OF) indicates when the converter is
overranged or underranged. In CMOS mode, a logic high on
the OFA pin indicates an overflow or underflow on the A data
bus, while a logic high on the OFB pin indicates an overflow
on the B data bus. In LVDS mode, a differential logic high
on OF⁺/OF^– pins indicates an overflow or underflow.
LTM9001
V_DD
DATA
FROM
LATCH
PREDRIVER
LOGIC
3.5mA
OV_DD
3.3V
V_DD
10k
OV_DD
43Ω
10k
OV_DD
100Ω
43Ω
LVDS
RECEIVER
+
1.20V –
OGND
9001 F11
Figure 11. Equivalent Output Buffer in LVDS Mode
9001fc
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