LTC4009-2_15 Datasheet, PDF (22/28 Pages) Linear Technology – High Efficiency, Multi-Chemistry Battery Charger

LTC4009
LTC4009-1/LTC4009-2
Applications Information
where Q_G is the rated gate charge of the top external NFET
with V_GS = 4.5V. The maximum average diode current is
then given by:
I_D = Q_G • 665kHz
To improve efficiency by increasing V_GS applied to the top
FET, substitute a Schottky diode with low reverse leakage
for D1.
PWM jitter has been observed in some designs operating
at higher V_IN/V_OUT ratios. This jitter does not substantially
affect DC charge current accuracy. A series resistor with a
value of 5Ω to 20Ω can be inserted between the cathode
of D1 and the BOOST pin to remove this jitter if present.
A resistor case size of 0603 or larger is recommended to
lower ESL and achieve the best results.
FET Selection
Two external power MOSFETs must be selected for use
with the charger: an N-channel power switch (top FET)
and an N-channel synchronous rectifier (bottom FET).
Peak gate-to-source drive levels are internally set to about
5V. Consequently, logic-level FETs must be used. In addi-
tion to the fundamental DC current, selection criteria for
these MOSFETs also include channel resistance R_DS(ON),
total gate charge Q_G, reverse transfer capacitance C_RSS,
maximum rated drain-source voltage BV_DSS and switching
characteristics such as t_d(ON/OFF). Power dissipation for
each external FET is given by:
( ) _PD(TOP)
=
V_BAT
• I_MAX2
• 1+
V_CLP
δ∆T
R_DS(ON)
+ k • V_CLP2 • I_MAX • C_RSS • 665kHz
( ) ( ) _{PD(BOT) =}
V_CLP – V_BAT
• I_MAX2 • 1+ δ∆T R_DS(ON)
V_CLP
where δ is the temperature dependency of R_DS(ON), ΔT
is the temperature rise above the point specified in the
FET data sheet for R_DS(ON) and k is a constant inversely
related to the internal LTC4009 top gate driver. The term
(1 + δΔT) is generally given for a MOSFET in the form
of a normalized R_DS(ON) curve versus temperature, but
δ of 0.005/°C can be used as a suitable approximation
for logic-level FETs if other data is not available. C_RSS =
Q_GD/dV_DS is usually specified in the MOSFET character-
istics. The constant k = 2 can be used in estimating top
FET dissipation. The LTC4009 is designed to work best
with external FET switches with a total gate charge at 5V
of 15nC or less.
For V_CLP < 20V, high charge current efficiency generally
improves with larger FETs, while for V_CLP > 20V, top gate
transition losses increase rapidly to the point that using
a topside NFET with higher R_DS(ON) but lower C_RSS can
actually provide higher efficiency. If the charger will be
operated with a duty cycle above 85%, overall efficiency
is normally improved by using a larger top FET.
The synchronous (bottom) FET losses are greatest at high
input voltage or during a short circuit, which forces a low
side duty cycle of nearly 100%. Increasing the size of this
FET lowers its losses but increases power dissipation in the
LTC4009. Using asymmetrical FETs will normally achieve
cost savings while allowing optimum efficiency.
Select FETs with BV_DSS that exceeds the maximum V_CLP
voltage that will occur. Both FETs are subjected to this level
of stress during operation. Many logic-level MOSFETs are
limited to 30V or less.
4009fd
22