LTC3850-1_15 Datasheet, PDF (22/38 Pages) Linear Technology – Dual, 2-Phase Synchronous Step-Down Switching Controller

LTC3850/LTC3850-1
APPLICATIONS INFORMATION
suggested. A 2.2Ω – 10Ω resistor placed between C_IN
(C1) and the V_IN pin provides further isolation between
the two channels.
The selection of C_OUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆V_OUT) is approximated by:
∆V_OUT
≈ I_RIPPLE
 _ESR
+
1
8fC_OUT


where f is the operating frequency, C_OUT is the output
capacitance and I_RIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since I_RIPPLE increases with input voltage.
Setting Output Voltage
The LTC3850 output voltages are each set by an external
feedback resistive divider carefully placed across the out-
put, as shown in Figure 9. The regulated output voltage
is determined by:
V_OUT
=
0.8V
•


1+
R_B
R_A


To improve the frequency response, a feed-forward ca-
pacitor, C_FF, may be used. Great care should be taken to
route the V_FB line away from noise sources, such as the
inductor or the SW line.
V_OUT
1/2 LTC3850
V_FB
R_B
C_FF
R_A
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Figure 9. Setting Output Voltage
Fault Conditions: Current Limit and Current Foldback
The LTC3850 includes current foldback to help limit load
current when the output is shorted to ground. If the out-
put falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from its
maximum programmed value to one-third of the maximum
value. Foldback current limiting is disabled during the
22
soft-start or tracking up. Under short-circuit conditions
with very low duty cycles, the LTC3850 will begin cycle
skipping in order to limit the short-circuit current. In this
situation the bottom MOSFET will be dissipating most of
the power but less than in normal operation. The short-
circuit ripple current is determined by the minimum on-
time t_ON(MIN) of the LTC3850 (≈ 90ns), the input voltage
and inductor value:
∆I_L(SC)
=
t_ON(MIN)
•
V_IN
L
The resulting short-circuit current is:
I_SC
=
1/3
V_{SENSE(MAX )}
R_SENSE
–
1
2
∆I_L(SC)
Phase-Locked Loop and Frequency Synchronization
The LTC3850 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (V_CO) and a phase
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The turn-on
of controller 2’s top MOSFET is thus 180 degrees out-
of-phase with the external clock. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the FREQ/PLLFLTR pin. The
relationship between the voltage on the FREQ/PLLFLTR
pin and operating frequency is shown in Figure 10 and
specified in the Electrical Characteristics table. Note that
the LTC3850 can only be synchronized to an external clock
whose frequency is within range of the LTC3850’s internal
V_CO. This is guaranteed to be between 250kHz and 780kHz.
A simplified block diagram is shown in Figure 11.
If no clock is applied to MODE/PLLIN pin, the FREQ/
PLLFLTR pin will be high impedance.
If the external clock frequency is greater than the internal
oscillator’s frequency, f_OSC, then current is sourced con-
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