LTC3704_15 Datasheet, PDF (22/28 Pages) Linear Technology – Wide Input Range, No RSENSE Positive-to-Negative DC/DC Controller

LTC3704
APPLICATIO S I FOR ATIO
V_OUT (AC)
10mV/DIV
V_OUT (AC)
100mV/DIV
I_L2 (DC)
1A/DIV
I_OUT (DC)
1A/DIV
2A
0.5A
V_IN = 5V
I_OUT = –2V
1μs/DIV
3704 F18
Figure 18. Output Ripple Voltage and
Inductor Current for the Circuit in Figure 15
V_IN = 5V
250μs/DIV
3704 F19
Figure 19. Load Step Response at V_IN = 5V
for the Circuit in Figure 15
V_OUT (AC)
100mV/DIV
I_OUT (DC)
1A/DIV
2A
0.5A
V_OUT
1V/DIV
I_OUT
1A/DIV
V_OUT
I_OUT
V_IN = 15V
250μs/DIV
3704 F20
Figure 20. Load Step Response at V_IN = 15V
for the Circuit in Figure 15
V_IN = 5V
1ms/DIV
3704 F21
Figure 21. Soft-Start for the Circuit in Figure 15
The capacitor used was a TDK 47μF, 16V X5R-dielectric
ceramic (C5750X5R1C476M), mainly because of its low
ESR (2.4mΩ) and high RMS current capability.
8. The peak-to-peak output ripple is:
ΔV_O(P−P)
=
1– D_MAX
f
•
V_O
L2
⎡
⎢^–ESR
⎣
–
8
•
1
f •C_O
⎤
⎥
⎦
As a first try, a TDK 100μF, 6.3V X5R-dielectric ceramic
capacitor was chosen (C5750X5R0J107M). This capaci-
tor has a very low 1.6mΩ of ESR. As a result, the peak-to-
peak output ripple voltage is:
22
ΔV_O(P−P)
=
1– 0.5
300k
•
5.0
3.5μ
⎡
⎢^–0.0016
⎣
–
8
•
1
⎤
300k
•
100μ
⎥
⎦
=
13.7mV
This ripple voltage calculation also assumes no coupling
between the inductors, making the 13.7mV number very
conservative.
Figure 15 illustrates the same basic application shown in
Figure 1, with the added features of soft-start and
undervoltage lockout on the input supply. Figures 16
through 21 illustrate the measured performance for this
converter. The peak efficiency is 87% at a load current of
2A and the peak-to-peak output ripple is less than 10mV.
Figures 19 and 20 illustrate the load step response at 5V
and 15V input, and Figure 21, the start-up characteristics
with a resistive load.
3704fb