LTC3415 Datasheet, PDF (22/28 Pages) Linear Technology – 7A, PolyPhase Synchronous Step-Down Regulator

LTC3415
APPLICATIONS INFORMATION
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3415. Check the following in your layout:
1) Do the capacitors C_IN connect to the power PV_IN and
power PGND as closely as possible? These capacitors
provide the AC current to the internal power MOSFETs
and their drivers.
2) Are the C_OUT and L1 closely connected? The (–) plate
of C_OUT returns current to PGND and the (–) plate of
C_IN.
3) The resistive divider, R1 and R2, must be connected
between the (+) plate of C_OUT and a ground line termi-
nated near SGND. The feedback signal V_FB should be
routed away from noisy components and traces, such
as the SW line, and its trace should be minimized.
4) Keep sensitive components away from the SW pin. The
input capacitor C_IN, the compensation capacitor C_C and
C_ITH and all the resistors R1, R2, R_C should be routed
away from the SW trace and the inductor L1.
5) A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the SGND pin at one
point which is then connected to the PGND pin.
Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected to
one of the input supplies: PV_IN, PGND, SV_IN, or SGND.
Design Example
As a design example, consider using the LTC3415 in an
application with the following specifications:
V_IN = 3.3V, V_OUT = 1.8V, I_OUT(MAX) = 7A,
I_OUT(MIN) = 500mA, f = 1.5MHz
Because efficiency is important at both high and low load
current, Burst Mode operation or pulse-skipping operation
will be utilized. First calculate the inductor value for about
40% ripple current at maximum V_IN:
L
=



1.8V
1.5MHz • 2.8A

_1–
1.8V
3.3V


=
0.2μH
C_OUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
100μF ceramic capacitors will be used.
C_IN should be sized for a maximum current rating of:
I_RMS
=
7A



2.5V
4.2V


4.2V _{– 1 = 3.43A}
2.5V
Decoupling the PV_IN pins with three 47μF ceramic capaci-
tors is adequate for most applications.
3415fa
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