LTC3415 Datasheet, PDF (12/28 Pages) Linear Technology – 7A, PolyPhase Synchronous Step-Down Regulator

LTC3415
OPERATION
Phase-Locked-Loop Operation
In order to synchronize to an external signal, the LTC3415
has an internal phase-locked-loop comprised of an in-
ternal voltage controlled oscillator and phase detector.
This allows the top P-channel power MOSFET turn-on to
be locked to the rising edge of an external source. The
frequency range of the voltage controlled oscillator is
+50% around the center frequency. Leaving the PLLLPF
pin floating corresponds to a free-running frequency of
approximately 1.5MHz. Tying PLLLPF directly to SV_IN
corresponds to 1.33x of center frequency (2MHz) while
tying PLLLPF to ground corresponds to 0.67x of center
frequency (1MHz).
The phase detector used is an edge sensitive digital type
which provides zero degree phase shift between the external
and internal oscillators. The output of the phase detector
is a complementary pair of current sources charging or
discharging the external filter network on the PLLLPF pin.
See Figure 6.
If the external frequency, CLKIN, is greater than the os-
cillator frequency f_OSC, current is sourced continuously,
pulling up the PLLLPF pin. When the external frequency is
less than f_OSC, current is sunk continuously, pulling down
the PLLLPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus the voltage on the PLLLPF pin
is adjusted until the phase and frequency of the external
and internal oscillators are identical. The CLKIN pin must
be driven from a low impedance source such as a logic
gate located close to the pin. The loop filter components
(C_LP, R_LP) smooth out the current pulses from the phase
detector and provide a stable input to the voltage controlled
oscillator. The filter components determine how fast the
loop acquires lock. Typically R_LP = 10k and C_LP is 100pf
to 1000pf.
The CLKOUT pin provides a signal to synchronize follow-
ing stages of LTC3415s. Its amplitude is 0V to 2V and its
phase with respect to the internal oscillator (or CLKIN) is
controlled by the PHMODE pin.
Internal/External I_TH Compensation
During single phase operation, the user can simplify the
loop compensation by tying the I_TH pin to SV_IN to enable
internal compensation. This connects an internal 50k
resistor in series with a 50pF cap to the output of the
error amplifier (internal I_TH compensation point). This is
a trade-off for simplicity instead of OPTI-LOOP^® optimiza-
tion, where I_TH components are external and are selected
to optimize the loop transient response with minimum
output capacitance. See Checking Transient Response in
the Applications Information section.
OPTI-LOOP is a registered trademark of Linear Technology Corporation.
2V
EXTERNAL
OSC
CLKIN
50k
PHASE
DETECTOR
DIGITAL
PHASE
FREQUENCY
DETECTOR
R_LP
10k
C_LP
PLLLPF
OSC
3415 F06
Figure 6. Phase-Locked-Loop Block Diagram
3415fa
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