LTC4008 Datasheet, PDF (20/24 Pages) Linear Technology – 4A, High Efficiency, Multi-Chemistry Battery Charger

LTC4008
APPLICATIO S I FOR ATIO
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall
times should be minimized. To prevent magnetic and
electrical field radiation and high frequency resonant prob-
lems, proper layout of the components connected to the IC
is essential. (See Figure 11.) Here is a PCB layout priority
list for proper layout. Layout the PCB using this specific
order.
1. Input capacitors need to be placed as close as possible
to switching FET’s supply and ground connections.
Shortest copper trace connections possible. These
parts must be on the same layer of copper. Vias must
not be used to make this connection.
2. The control IC needs to be close to the switching FET’s
gate terminals. Keep the gate drive signals short for a
clean FET drive. This includes IC supply pins that con-
nect to the switching FET source pins. The IC can be
placed on the opposite side of the PCB relative to above.
3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in
parallel. Minimize capacitance from this node to any
other trace or plane.
4. Place the output current sense resistor right next to
the inductor output but oriented such that the IC’s
current sense feedback traces going to resistor are not
long. The feedback traces need to be routed together
as a single pair on the same layer at any given time with
smallest trace spacing possible. Locate any filter
component on these traces next to the IC and not at the
sense resistor location.
5. Place output capacitors next to the sense resistor
output and ground.
6. Output capacitor ground connections need to feed
into same copper that connects to the input capacitor
ground before tying back into system ground.
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