LTC3851A-1_15 Datasheet, PDF (20/30 Pages) Linear Technology – Synchronous Step-Down Switching Regulator Controller

LTC3851A-1
Applications Information
Fault Conditions: Current Limit and Current Foldback
The LTC3851A-1 includes current foldback to help limit
load current when the output is shorted to ground. If the
output falls below 40% of its nominal output level, the
maximum sense voltage is progressively lowered from
its maximum programmed value to about 25% of the
that value. Foldback current limiting is disabled during
soft-start or tracking. Under short-circuit conditions
with very low duty cycles, the LTC3851A-1 will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short-circuit ripple current is determined by the minimum
on-time, t_ON(MIN), of the LTC3851A-1 (≈90ns), the input
voltage and inductor value:
∆I_L(SC)
=
t_ON(MIN)
•
V_IN
L
The resulting short-circuit current is:
I_SC
=
1/ 4Max V_SENSE
R_SENSE
–
1
2
∆I_L(SC)
Programming Switching Frequency
To set the switching frequency of the LTC3851A-1, connect
a resistor, R_FREQ, between FREQ/PLLFLTR and GND. The
relationship between the oscillator frequency and R_FREQ
is shown in Figure 7. A 0.1µF bypass capacitor should be
connected in parallel with R_FREQ.
750
700
650
600
550
500
450
400
350
300
250
20 40
60 80 100 120 140 160
R_FREQ (kΩ)
3851A1 F07
Figure 7. Relationship Between Oscillator Frequency
and Resistor Connected Between FREQ/PLLFLTR and GND
20
Phase-Locked Loop and Frequency Synchronization
The LTC3851A-1 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (V_CO) and a
phase detector. This allows the turn-on of the top MOSFET
to be locked to the rising edge of an external clock signal
applied to the MODE/PLLIN pin. This phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen­
tary current sources that charge or discharge the external
filter network connected to the FREQ/PLLFLTR pin. Note
that the LTC3851A-1 can only be synchronized to an
external clock whose frequency is within range of the
LTC3851A-1’s internal V_CO.This is guaranteed to be be-
tween 250kHz and 750kHz. A simplified block diagram is
shown in Figure 8.
If the external clock frequency is greater than the internal
oscillator’s frequency, f_OSC , then current is sunk con­
tinuously from the phase detector output, pulling down the
FREQ/PLLFLTR pin. When the external clock frequency is
less than f_OSC , current is sourced continuously, pulling up
the FREQ/PLLFLTR pin. If the external and internal frequen-
cies are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to the
phase difference. The voltage on the FREQ/PLLFLTR pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor C_LP holds the voltage.
2.7V
R_LP
C_LP
EXTERNAL
OSCILLATOR
MODE/
PLLIN
DIGITAL
PHASE/
FREQUENCY
DETECTOR
FREQ/PLLFLTR
VCO
3851A1 F08
Figure 8. Phase-Locked Loop Block Diagram
3851a1fa