LTC3731H_15 Datasheet, PDF (20/34 Pages) Linear Technology – 3-Phase, 600kHz, Synchronous Buck Switching Regulator Controller

LTC3731H
Applications Information
PHASE
DETECTOR/
2.4V
OSCILLATOR
EXTERNAL
OSC
OSC
PLLIN
DIGITAL
PHASE/
FREQUENCY
50k
DETECTOR
R_LP
10k
C_LP
PLLFLTR
3731H F09
Figure 9. Phase-Locked Loop Block Diagram
the PLLFLTR pin. If the external and internal frequencies
are the same, but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus, the voltage on the PLLFLTR pin
is adjusted until the phase and frequency of the external
and internal oscillators are identical. At this stable operat-
ing point, the phase comparator output is open and the
filter capacitor C_LP holds the voltage. The IC PLLIN pin
must be driven from a low impedance source such as a
logic gate located close to the pin. When using multiple
ICs for a phase-locked system, the PLLFLTR pin of the
master oscillator should be biased at a voltage that will
guarantee the slave oscillator(s) ability to lock onto the
master’s frequency. A voltage of 1.7V or below applied to
the master oscillator’s PLLFLTR pin is recommended in
order to meet this requirement. The resultant operating
frequency will be approximately 550kHz for 1.7V.
The loop filter components (C_LP, R_LP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C_LP and R_LP determine how fast the loop
acquires lock. Typically R_LP =10k and C_LP ranges from
0.01µF to 0.1µF.
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN), is the smallest time duration
that the IC is capable of turning on the top MOSFET. It is
determined by internal timing delays and the gate charge
of the top MOSFET. Low duty cycle applications may ap-
proach this minimum on-time limit and care should be
taken to ensure that:
t_ON(MIN)
<
V_OUT
V_IN(f₎
If the duty cycle falls below what can be accommodated
by the minimum on-time, the IC will begin to skip every
other cycle, resulting in half-frequency operation. The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on-time for the IC is generally about 110ns.
However, as the peak sense voltage decreases the minimum
on-time gradually increases. This is of particular concern
in forced continuous applications with low ripple current
at light loads. If the duty cycle drops below the minimum
on-time limit in this situation, a significant amount of cycle
skipping can occur with correspondingly larger current
and voltage ripple.
If an application can operate close to the minimum on-time
limit, an inductor must be chosen that is low enough in
value to provide sufficient ripple amplitude to meet the
minimum on-time requirement. As a general rule, keep
the inductor ripple current for each channel equal to or
greater than 30% of I_OUT(MAX) at V_IN(MAX).
3731Hfb
20