LTC3731H_15 Datasheet, PDF (14/34 Pages) Linear Technology – 3-Phase, 600kHz, Synchronous Buck Switching Regulator Controller

LTC3731H
Applications Information
MOSFET in applications that have an output voltage that
is less than 1/3 of the input voltage. In applications where
V_IN >> V_OUT, the top MOSFETs’ on-resistance is normally
less important for overall efficiency than its input capaci-
tance at operating frequencies above 300kHz. MOSFET
manufacturers have designed special purpose devices that
provide reasonably low on-resistance with significantly
reduced input capacitance for the main switch application
in switching regulators.
The peak-to-peak MOSFET gate drive levels are set by the
voltage, V_CC, requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BV_DSS specification for the MOSFETs as well; many of the
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the
on‑resistance R_DS(ON), input capacitance, input voltage
and maximum output current.
MOSFET input capacitance is a combination of sev-
eral components but can be taken from the typical “gate
charge” curve included on most data sheets (Figure 5).
The curve is generated by forcing a constant input cur-
rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given V_DS drain
V_IN
MILLER EFFECT
V_GS
a
b
Q_IN
C_MILLER = (Q_B – Q_A)/V_DS
V
+
V_G–S
+
– ^VDS
3731H F05
Figure 5. Gate Charge Characteristic
voltage, but can be adjusted for different V_DS voltages by
multiplying by the ratio of the application V_DS to the curve
specified V_DS values. A way to estimate the C_MILLER term
is to take the change in gate charge from points a and b
on a manufacturers data sheet and divide by the stated
V_DS voltage specified. C_MILLER is the most important se-
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. C_RSS and C_OS are specified sometimes but
definitions of these parameters are not included.
When the controller is operating in continuous mode
the duty cycles for the top and bottom MOSFETs are
given by:
Main Switch Duty Cycle = ^VOUT
V_IN
Synchronous
Switch
Duty
Cycle
=


V_IN
– V_OUT
V_IN


The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
( ) ^P_MAIN
=
V_OUT
V_IN

I_MAX
N

2
1+ d
R_DS(ON)
+
V_IN2
I_MAX
2N
(^R_DR)(^C
) _MILLER
•
( ) ^


V_CC
1
– V_TH(IL)
+
1^
V_TH(IL)


f
( ) ^P_SYNC
=
V_IN
– V_OUT
V_IN

I_MAX
N

2
1+ d
R_DS(ON)
where N is the number of output stages, d is the tem-
perature dependency of R_DS(ON), R_DR is the effective top
driver resistance (approximately 2Ω at V_GS = V_MILLER), V_IN
is the drain potential and the change in drain potential in
the particular application. V_TH(IL) is the data sheet speci-
fied typical gate threshold voltage specified in the power
MOSFET data sheet at the specified drain current. C_MILLER
is the calculated capacitance using the gate charge curve
from the MOSFET data sheet and the technique described
above.
3731Hfb
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