LTC3630 Datasheet, PDF (20/26 Pages) Linear Technology – High Efficiency, 65V 500mA Synchronous

LTC3630
APPLICATIONS INFORMATION
Pin Clearance/Creepage Considerations
The LTC3630 is available in two packages (MSE16 and
DHC) both with identical functionality. However, the 0.2mm
(minimum space) between pins and paddle on the DHC-
package may not provide sufficient PC board trace clearance
between high and low voltage pins in some higher voltage
applications. In applications where clearance is required,
the MSE16 package should be used. The MSE16 package
has removed pins between all the adjacent high voltage
and low voltage pins, providing 0.657mm clearance which
will be sufficient for most applications. For more informa-
tion, refer to the printed circuit board design standards
described in IPC-2221 (www.ipc.org).
L1
V_IN
V_IN
SW
V_OUT
R3
R1
RUN V_FB
R4 LTC3630
I_SET
C_IN
R_ISET ^R2
C_ISET
C_OUT
C_SS
FBO
SS
V_PRG2
V_PRG1
GND
V_IN
5V TO 65V
C_IN
4.7μF
V_IN
SW
LTC3630
RUN V_FB
I_SET
SS
FBO V_PRG1
V_PRG2
GND
3630 F13
L1
33μH
R_ISET
220k
C_IN: TDK C5750X7R2A-475M (2220)
C_OUT: 2 wAVX 1812D107MAT
L1: SUMIDA CDRH105RNP-330N
C_OUT
100μF
w2
V_OUT
5V
500mA
C_ISET
100pF
Figure 13. 5V to 65V Input to 5V Output,
High Efficiency, 500mA Regulator
L1
C_IN
V_IN
V_OUT
C_OUT
GND
VIAS TO GROUND PLANE
OUTLINE OF LOCAL GROUND PLANE
3630 F12
Figure 12. Example PCB Layout
3630fb
20