LTC3637_15 Datasheet, PDF (19/26 Pages) Linear Technology – 76V, 1A Step-Down Regulator

LTC3637
APPLICATIONS INFORMATION
Note that the V_IN falling thresholds for both UVLO and
OVLO will be 10% less than the rising thresholds or 5.4V
and 43V respectively.
The absolute maximum rating on the OVLO pin (6V) is
not violated based on the following:
OVLO(MAX)
=
80V
•
(806k
+
24.9k
174k +
24.9k)
=
2V
The I_SET pin should be left open in this example to select
maximum peak current (2.4A typical). Figure 11 shows a
complete schematic for this design example.
V_IN
24V
V_IN
SW
4.7µH
V_OUT
3.3V
1A
806k
LTC3637
2.2µF 174k
RUN
V_FB
SS
V_PRG2
100µF
OVLO V_PRG1
24.9k ^FBO
I_SET
GND
3637 F11
V_IN
V_IN
SW
R3
RUN V_FB
R4 LTC3637
OVLO I_SET
C_{IN R5}
L1
D1
R1
V_OUT
R_ISET ^R2
C_ISET
C_OUT
C_SS
FBO
SS
V_PRG2
V_PRG1
L1
C_OUT
C_IN
Figure 11. 24V to 3.3V, 1A Regulator at 200kHz
D1
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3637. Check the following in your layout:
1. Large switched currents flow in the power switches
and input capacitor. The loop formed by these compo-
nents should be as small as possible. A ground plane
is recommended to minimize ground impedance.
2. Connect the (+) terminal of the input capacitor, C_IN, as
close as possible to the V_IN pin. This capacitor provides
the AC current into the internal power MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small signal nodes. The rapid transitions on the switching
node can couple to high impedance nodes, in particular
V_FB, and create increased output ripple.
4. Flood all unused area on all layers with copper except
for the area under the inductor. Flooding with copper
will reduce the temperature rise of power components.
You can connect the copper areas to any DC net (V_IN,
V_OUT, GND, or any other DC rail in your system).
VIAS TO GROUND PLANE
3637 F12
Figure 12. Example PCB Layout
Pin Clearance/Creepage Considerations
The LTC3637 is available in two packages (MSE16 and
DHC) both with identical functionality. However, the 0.2mm
(minimum space) between pins and paddle on the DHC
package may not provide sufficient PC board trace clear-
ance between high and low voltage pins in some higher
voltage applications. In applications where clearance is
required, the MSE16 package should be used. The MSE16
package has removed pins between all the adjacent high
voltage and low voltage pins, providing 0.657mm clear-
ance which will be sufficient for most applications. For
more information, refer to the printed circuit board design
standards described in IPC-2221 (www.ipc.org).
3637fa
For more information www.linear.com/LTC3637
19