LTC3417A-2_15 Datasheet, PDF (19/20 Pages) Linear Technology – Dual Synchronous 1.5A/1A 4MHz Step-Down DC/DC Regulator

PACKAGE DESCRIPTION
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
LTC3417A-2
0.65 ± 0.05
5.00 ± 0.10
(2 SIDES)
9
R = 0.20
TYP
R = 0.115
TYP
0.40 ± 0.10
16
3.50 ± 0.05
1.65 ± 0.05
2.20 ± 0.05 (2 SIDES)
PACKAGE
OUTLINE
3.00 ± 0.10 1.65 ± 0.10
(2 SIDES) (2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
8
1
0.25 ± 0.05
0.50 BSC
0.200 REF
0.75 ± 0.05
0.25 ± 0.05
0.50 BSC
4.40 ± 0.05
(2 SIDES)
0.00 – 0.05
4.40 ± 0.10
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
PIN 1
NOTCH
(DHC16) DFN 1103
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CA
4.95
(.195)
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
20 1918 17 16 15 14 1312 11
6.60 ± 0.10
4.50 ± 0.10
SEE NOTE 4
2.74
(.108)
0.45 ± 0.05
1.05 ± 0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
2.74
(.108)
6.40
(.252)
BSC
1 2 3 4 5 6 7 8 9 10
1.20
(.047)
MAX
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2.
DIMENSIONS
ARE
IN
MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE20 (CA) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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