LTC2122_15 Datasheet, PDF (19/50 Pages) Linear Technology – Dual 14-Bit 170Msps ADC with JESD204B Serial Outputs

APPLICATIONS INFORMATION
0.1µF
IN
10Ω
4.7Ω
0.1µF
V_CM
LTC2122
A_IN+
45Ω
100Ω
0.1µF
45Ω
0.1µF
T1: MABA
4.7Ω
A_IN–
007159-000000
2122 F05
Figure 5. Recommended Front-End Circuit for
Input Frequencies from 150MHz to 900MHz
INPUT
50Ω 50Ω
0.1µF
0.1µF
4.7Ω
4.7Ω
V_CM
0.1µF
LTC2122
3pF
A_IN+
3pF
A_IN–
3pF
2122 F06
Figure 6. Front-End Circuit Using a
High Speed Differential Amplifier
V_REF
2.2µF
SENSE
5Ω
1.25V
LTC2122
SCALER/
BUFFER
ADC
REFERENCE
SENSE
DETECTOR
2122 F07
Figure 7. Reference Circuit
LTC2122
Amplifier Circuits
Figure 6 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures 3
through 5) should convert the signal to differential before
driving the A/D. The A/D cannot be driven single-ended.
Reference
The LTC2122 has an internal 1.25V voltage reference. For
a 1.5V input range with internal reference, connect SENSE
to V_DD. For a 1.5V input range with an external reference,
apply a 1.25V reference voltage to SENSE (Figure 7).
Device Clock (DEVCLK) Input
The DEVCLK is used to derive the ADC sample clock, so
the signal quality of the DEVCLK inputs strongly affects
the A/D noise performance. The DEVCLK inputs should
be treated as analog signals. Do not route them next to
digital traces on the circuit board. The DEVCLK inputs are
internally biased to 1.2V through 10k equivalent resistance
(Figure 8).
LTC2122
V_DD
1.2V
10k 10k
DEVCLK⁺
DEVCLK^–
2122 F08
Figure 8. Equivalent DEVCLK Input Circuit
For more information www.linear.com/LTC2122
2122fa
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