LTC2122_15 Datasheet, PDF (1/50 Pages) Linear Technology – Dual 14-Bit 170Msps ADC with JESD204B Serial Outputs

LTC2122
Dual 14-Bit 170Msps ADC
with JESD204B Serial Outputs
FEATURES
n _{6.0Gbps JESD204B Interface}
n _{Only One Output Lane Required for Both ADCs}
(F_S < = 150Msps)
n _{70dBFS SNR}
n _{90dBFS SFDR}
n _{Low Power: 751mW Total}
n _{Single 1.8V Supply}
n _{Easy to Drive 1.5VP-P Input Range}
n _{1.25GHz Full Power Bandwidth S/H}
n _{Optional Clock Divide by Two}
n _{Optional Clock Duty Cycle Stabilizer}
n _{Low Power Sleep and Nap Modes}
n _{Serial SPI Port for Configuration}
n _{48-Lead (7mm × 7mm) QFN Package}
APPLICATIONS
n _{Communications}
n _{Cellular Base Stations}
n _{Software Defined Radios}
n _{Medical Imaging}
n _{High Definition Video}
n _{Test and Measurement Instrumentation}
DESCRIPTION
The LTC^®2122 is a 2-channel simultaneous sampling
170Msps 14-bit A/D converter with serial JESD204B
outputs. It is designed for digitizing high frequency,
wide dynamic range signals. It is perfect for demanding
communications applications with AC performance that
includes 70dBFS SNR and 90dBFS spurious free dynamic
range (SFDR). The 1.25GHz input bandwidth allows the
ADC to under-sample high frequencies.
The JESD204B serial interface simplifies the PCB design by
minimizing the number of data lines required. At 170Msps,
only two 3.4Gbps output lanes are required. For sample
rates up to 150Msps, both ADCs may share the same
output lane at up to 6.0Gbps.
The DEVCLK⁺ and DEVCLK^– inputs can be driven differ-
entially with sine wave, PECL, or LVDS signals. An optional
clock divide-by-two circuit or clock duty cycle stabilizer
maintains high performance at full speed for a wide range
of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
ANALOG
INPUT
14-BIT ADC
LTC2122
JESD204B
LOGIC
SERIALIZER
CLOCK
(170MHz OR
340MHz)
ANALOG
INPUT
CLOCK
÷ 2 OR ÷ 1
PLL
14-BIT ADC
JESD204B
LOGIC
SERIALIZER
OV_DD
1.2V TO 1.9V
50Ω 50Ω
3.4Gbps
OV_DD
1.2V TO 1.9V
JESD204B
FPGA OR ASIC
50Ω 50Ω
3.4Gbps
For more information www.linear.com/LTC2122
64k Point 2-Tone FFT,
f_IN = 71MHz and 69MHz,
–7dBFS, 170Msps
0
–20
–40
–60
–80
–100
–120
0
10 20 30 40 50 60 70 80
FREQUENCY (MHz)
2122 TA01a
2122 TA01
2122fa
1