LTC3703_15 Datasheet, PDF (18/34 Pages) Linear Technology – 100V Synchronous Switching Regulator Controller

LTC3703
Applications Information
Bottom MOSFET Source Supply (BGRTN)
The bottom gate driver, BG, switches from DRV_CC to
BGRTN where BGRTN can be a voltage between ground
and –5V. Why not just keep it simple and always connect
BGRTN to ground? In high voltage switching converters,
the switch node dV/dt can be many volts/ns, which will
pull up on the gate of the bottom MOSFET through its
Miller capacitance. If this Miller current, times the internal
gate resistance of the MOSFET plus the driver resistance,
exceeds the threshold of the FET, shoot-through will oc-
cur. By using a negative supply on BGRTN, the BG can be
pulled below ground when turning the bottom MOSFET off.
This provides a few extra volts of margin before the gate
reaches the turn-on threshold of the MOSFET. Be aware
that the maximum voltage difference between DRV_CC and
BGRTN is 15V. If, for example, V_BGRTN = –2V, the maximum
voltage on DRV_CC pin is now 13V instead of 15V.
Current Limit Programming
Programming current limit on the LTC3703 is straight
forward. The I_MAX pin sets the current limit by setting
the maximum allowable voltage drop across the bottom
MOSFET. The voltage across the MOSFET is set by its on-
resistance and the current flowing in the inductor, which
is the same as the output current. The LTC3703 current
limit circuit inverts the negative voltage across the MOSFET
before comparing it to the voltage at I_MAX, allowing the
current limit to be set with a positive voltage.
To set the current limit, calculate the expected voltage
drop across the bottom MOSFET at the maximum desired
current and maximum junction temperature:
V_PROG = (I_LIMIT)(R_DS(ON))(1 + δ)
where δ is explained in the MOSFET Selection section.
V_PROG is then programmed at the I_MAX pin using the
internal 12µA pull-up and an external resistor:
R_IMAX = V_PROG/12µA
The current limit value should be checked to ensure
that I_LIMIT(MIN) > I_OUT(MAX) and also that I_LIMIT(MAX) is
less than the maximum rated current of the inductor
and bottom MOSFET. The minimum value of current
limit generally occurs with the largest V_IN at the highest
18
ambient temperature, conditions that cause the largest
power loss in the converter. Note that it is important to
check for self-consistency between the assumed MOSFET
junction temperature and the resulting value of I_LIMIT which
heats the MOSFET switches.
Caution should be used when setting the current limit based
upon the R_DS(ON) of the MOSFETs. The maximum current
limit is determined by the minimum MOSFET on-resistance.
Data sheets typically specify nominal and maximum values
for R_DS(ON), but not a minimum. A reasonable assumption
is that the minimum R_DS(ON) lies the same amount below
the typical value as the maximum lies above it. Consult the
MOSFET manufacturer for further guidelines.
For best results, use a V_PROG voltage between 100mV and
500mV. Values outside of this range may give less accu-
rate current limit. The current limit can also be disabled
by floating the I_MAX pin.
FEEDBACK LOOP/COMPENSATION
Feedback Loop Types
In a typical LTC3703 circuit, the feedback loop consists of
the modulator, the external inductor, the output capacitor
and the feedback amplifier with its compensation network.
All of these components affect loop behavior and must be
accounted for in the loop compensation. The modulator
consists of the internal PWM generator, the output MOS-
FET drivers and the external MOSFETs themselves. From
a feedback loop point of view, it looks like a linear voltage
transfer function from COMP to SW and has a gain roughly
equal to the input voltage. It has fairly benign AC behavior
at typical loop compensation frequencies with significant
phase shift appearing at half the switching frequency.
The external inductor/output capacitor combination
makes a more significant contribution to loop behavior.
These components cause a second order LC roll off at the
output, with the attendant 180° phase shift. This rolloff is
what filters the PWM waveform, resulting in the desired
DC output voltage, but the phase shift complicates the
loop compensation if the gain is still higher than unity at
the pole frequency. Eventually (usually well above the LC
pole frequency), the reactance of the output capacitor will
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