LTC3630A Datasheet, PDF (18/24 Pages) Linear Technology – High Efficiency, 76V 500mA Synchronous Step-Down Converter

LTC3630A
Applications Information
Next, verify that this value meets the L_MIN requirement.
For this input voltage and peak current, the minimum
inductor value is:
L_MIN
=
24V • 150ns
1.2A
≅
3µH
R3
=
200k
which
is
≤
12V
40µA
R4
=
12V
–
200k • 1.21V
1.21V + 200k
•
4µA
=
20.9k
Therefore, the minimum inductor requirement is satisfied
and the 10μH inductor value may be used.
Next, C_IN and C_OUT are selected. For this design, C_IN should
be sized for a current rating of at least:
I_RMS
=
500mA
•
3.3V
24V
•
24V
3.3V
–
1
≅
175mA_RMS
Choose standard values for R3 = 200k, R4 = 21k. Note
that the V_IN falling threshold will be 10% less than the
rising threshold or 11V.
Since the maximum V_IN is more than 4.5x the UVLO thresh-
old, a 4.7V Zener diode in parallel with R4 is required to
keep the maximum voltage on the RUN pin less than the
absolute maximum of 6V.
The value of C_IN is selected to keep the input from droop-
ing less than 240mV (1%):
C_IN
>
10µH • 1.2A²
2 • 24V • 240mV
≅
2.2µF
C_OUT will be selected based on a value large enough to
satisfy the output voltage ripple requirement. For a 50mV
output ripple, the value of the output capacitor can be
calculated from:
C_OUT
>
10µH • 1.2A²
2 • 3.3V • 50mV
≅
47µF
C_OUT also needs an ESR that will satisfy the output voltage
ripple requirement. The required ESR can be calculated
from:
ESR < ^50mV ≅ 40mΩ
1.2A
The I_SET pin should be left open in this example to select
maximum peak current (1.2A typical). Figure 11 shows a
complete schematic for this design example.
V_IN
24V
10µH
V_IN
SW
200k
LTC3630A
V_OUT
3.3V
500mA
2.2µF
RUN
V_FB
SS
V_PRG2
47µF
4.7V
21k
V_PRG1
FBO
I_SET
GND
3630a F11
Figure 11. 24V to 3.3V, 500mA Regulator at 200kHz
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3630A. Check the following in your layout:
A 47µF ceramic capacitor has significantly less ESR than
40mΩ.
Since an output voltage of 3.3V is one of the standard
output configurations, the LTC3630A can be configured
by connecting V_PRG1 to ground and V_PRG2 to the SS pin.
The undervoltage lockout requirement on V_IN can be satis-
fied with a resistive divider from V_IN to the RUN pin (refer
to Figure 9). Calculate R3 and R4 as follows:
1. Large switched currents flow in the power switches and
input capacitor. The loop formed by these components
should be as small as possible. A ground plane is rec-
ommended to minimize ground impedance.
2. Connect the (+) terminal of the input capacitor, C_IN, as
close as possible to the V_IN pin. This capacitor provides
the AC current into the internal power MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small signal nodes. The rapid transitions on the switching
node can couple to high impedance nodes, in particular
V_FB, and create increased output ripple.
3630af
18
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