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LTC3616_15 Datasheet, PDF (18/28 Pages) Linear Technology – 6A, 4MHz Monolithic Synchronous Step-Down DC/DC Converter
LTC3616
Applications Information
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT , causing a rapid drop in VOUT . No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. More output
capacitance may be required depending on the duty cycle
and load step requirements.
AVP Mode
Fast load transient response, limited board space and low
cost are typical requirements of microprocessor power
supplies. A microprocessor has typical full load step with
very fast slew rate. The voltage at the microprocessor must
be held to about ±0.1V of nominal in spite of these load
current steps. Since the control loop cannot respond this
fast, the output capacitors must supply the load current
until the control loop can respond.
Normally, several capacitors in parallel are required to
meet microprocessor transient requirements. Capacitor
ESR and ESL primarily determine the amount of droop or
overshoot in the output voltage.
Consider the LTC3616 without AVP with a bank of tantalum
output capacitors. If a load step with very fast slew rate
occurs, the voltage excursion will be seen in both direc-
tions, for full load to minimum load transient and for the
minimum load to full load transient.
If the ITH pin is tied to SVIN, the active voltage position-
ing (AVP) mode and internal compensation are selected.
AVP mode intentionally compromises load regulation by
reducing the gain of the feedback circuit, resulting in an
output voltage that varies with load current. When the load
current suddenly increases, the output voltage starts from
a level slightly higher than nominal so the output voltage
can droop more and stay within the specified voltage
range. When the load current suddenly decreases the
output voltage starts at a level lower than nominal so the
output voltage can have more overshoot and stay within
the specified voltage range (see Figures 3 and 4).
The benefit is a lower peak-to-peak output voltage deviation
for a given load step without having to increase the output
filter capacitance. Alternatively, the output voltage filter
capacitance can be reduced while maintaining the same
peak to peak transient response. Due to the reduced loop
gain in AVP mode, no external compensation is required.
DDR Mode
The LTC3616 can both source and sink current if the MODE
pin is configured to forced continuous mode.
Current sinking is typically limited to 3A for 1MHz frequency
and a 0.47µH inductor, but can be lower at higher frequen-
cies and low output voltages. If higher ripple current can
be tolerated, smaller inductor values can increase the sink
current limit. See the Typical Performance Characteristics
curves for more information.
VOUT
200mV/DIV
VOUT
100mV/DIV
IL
1A/DIV
VIN = 3.3V
50µs/DIV
VOUT = 1.8V
ILOAD = 100mA TO 3A
VMODE = 1.5V
COMPENSATION FIGURE 1
3616 F03
Figure 3. Load Step Transient Forced
Continuous Mode (AVP Inactive)
IL
1A/DIV
VIN = 3.3V
50µs/DIV
VOUT = 1.8V
ILOAD = 100mA TO 3A
VMODE = 1.5V
VITH = 3.3V
OUTPUT CAPACITOR VALUE FIGURE 1
3616 F04
Figure 4. Load Step Transient Forced
Continuous Mode with AVP Mode
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