LTC3565_1 Datasheet, PDF (18/22 Pages) Linear Technology – 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter

LTC3565
Applications Information
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2µA with the 0.6V feedback voltage makes R1~300k. A close
standard 1% resistor value is 294k then R2 is 931k.
The compensation should be optimized for these compo-
nents by examining the load step response but a good place
to start for the LTC3565 is with a 12.1kΩ and 680pF filter.
The output capacitor may need to be increased depending
on the actual undershoot during a load step.
The PGOOD pin is a common drain output and requires a pull-
up resistor. A 100k resistor is used for adequate speed.
The circuit on page 1 of this data sheet shows the complete
schematic for this design example.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3565. These items are also illustrated graphically
in the layout diagram of Figure 4. Check the following in
your layout:
1. Does the capacitor C_IN connect to the power V_IN (Pin 6)
and power GND (Pin 5) as close as possible? This capacitor
provides the AC current to the internal power MOSFETs
and their drivers.
2. Are the C_OUT and L1 closely connected? The (–) plate of
C_OUT returns current to PGND and the (–) plate of C_IN.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C_OUT and a ground line. The
feedback signal V_FB should be routed away from noisy
components and traces, such as the SW line (Pin 4), and
its trace should be minimized.
4. Keep sensitive components away from the SW pin. The
input capacitor C_IN, the compensation capacitor C_C and
C_ITH and all the resistors R1, R2, R_T, and R_C should be
routed away from the SW trace and the inductor L1. The
SW pin pad should be kept as small as possible.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small signal
components returning to the GND pin at one point.
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. These copper areas should be connected to
one of the input supply rails: PV_IN, SV_IN or GND.
18
V_OUT
C_OUT
C_C
R_T
1
RT
R_C
ITH ¹⁰
2
RUN
LTC3565
V_FB ⁹
L1
3
SYNC/MODE
4
SW
5
PGOOD ⁸
SV_IN
7
6
GND
PV_IN
C_ITH
R1 R2
C4
R5
V_IN
3565 F06
C_IN
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 4. LTC3565 Layout Diagram (See Board Layout Checklist)
3565fa