LTC3417_15 Datasheet, PDF (18/20 Pages) Linear Technology – Dual Synchronous 1.4A/800mA 4MHz Step-Down DC/DC Regulator

LTC3417
APPLICATIONS INFORMATION
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3417. These items are also illustrated graphically
in the layout diagram of Figure 5. Check the following in
your layout.
1. Does the capacitor C_IN connect to the power V_IN1
(Pin 2), V_IN2 (Pin 8), and PGND2/GNDD (Pin 17) as
close as possible (DFN package)? It may be necessary
to split C_IN into two capacitors. This capacitor provides
the AC current to the internal power MOSFETs and
their drivers.
2. Are the C_OUT1, L₁ and C_OUT2, L₂ closely connected? The
(–) plate of C_OUT1 returns current to PGND1, and the
(–) plate of C_OUT2 returns current to the PGND2/GNDD
and the (–) plate of C_IN.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C_OUT1 and a ground line ter-
minated near GNDA. The resistor divider, R3 and R4,
must be connected between the (+) plate of C_OUT2 and
a ground line terminated near GNDA. The feedback
signals V_FB1 and V_FB2 should be routed away from noise
components and traces, such as the SW lines, and its
trace should be minimized.
4. Keep sensitive components away from the SW pins.
The input capacitor C_IN, the compensation capacitors
C_C1, C_C2, C_ITH1 and C_ITH2 and all resistors R1, R2, R3,
R4, R_ITH1 and R_ITH2 should be routed away from the
SW traces and the inductors L1 and L2.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GNDA pin at one
point which is then connected to the PGND2/GNDD
pin.
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to one of the input supplies.
V_IN
C_IN
10μF
C_IN2
0.1μF
C_OUT2
V_OUT2
STAR TO
GNDA
V_IN
L2
C_C2
R3
R4
R_ITH2
C_ITH2
R8
V_IN2
PGND2/
EXPOSED PAD
GNDA
V_IN1
PGND1
SW2
SW1
V_FB2 ^LTC3417 V_FB1
I_TH2
PGOOD
I_TH1
FREQ
C_IN1
0.1μF
L1
C_C1
R1
R2
R_ITH1
R7
C_ITH1
RUN2
PHASE
GNDD
RUN1
MODE
C_OUT1
V_OUT1
STAR TO
GNDA
V_IN
Figure 5
3417fd
18