LTC3417_15 Datasheet, PDF (14/20 Pages) Linear Technology – Dual Synchronous 1.4A/800mA 4MHz Step-Down DC/DC Regulator

LTC3417
APPLICATIONS INFORMATION
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V_OUT im-
mediately shifts by an amount equal to ΔI_LOAD • ESR_COUT,
where ESR_COUT is the effective series resistance of C_OUT.
ΔI_LOAD also begins to charge or discharge C_OUT generat-
ing a feedback error signal used by the regulator to return
V_OUT to its steady-state value. During this recovery time,
V_OUT can be monitored for overshoot or ringing that would
indicate a stability problem.
The initial output voltage step may not be within the band-
width of the feedback loop, so the standard second order
overshoot/DC ratio cannot be used to determine phase
margin. The gain of the loop increases with R_ITH and the
bandwidth of the loop increases with decreasing C_ITH. If
R_ITH is increased by the same factor that C_ITH is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, feedforward capacitors,
C1 and C2, can be added to improve the high frequency
response, as shown in Figure 4. Capacitor C1 provides
phase lead by creating a high frequency zero with R1
which improves the phase margin for the 1.4A SW1 chan-
nel. Capacitor C2 provides phase lead by creating a high
frequency zero with R3 which improves the phase margin
for the 800mA SW2 channel.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage V_IN drops toward V_OUT, the load step capability
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta, or single inductor, positive buck boost.
In some applications, a more severe transient can be
caused by switching in loads with large (>1μF) input ca-
pacitors. The discharged input capacitors are effectively
put in parallel with C_OUT, causing a rapid drop in V_OUT. No
regulator can deliver enough current to prevent this prob-
lem, if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A Hot Swap™ controller
is designed specifically for this purpose and usually in-
corporates current limiting, short-circuit protection, and
soft- starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100% – (P1+ P2 + P3 +…)
where P1, P2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources account for most of the losses
in LTC3417 circuits: 1) LTC3417 I_S current, 2) switching
losses, 3) I²R losses, 4) other losses.
1) The I_S current is the DC supply current given in the elec-
trical characteristics which excludes MOSFET driver and
control currents. I_S current results in a small (< 0.1%)
loss that increases with V_IN, even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge moves from
V_IN to ground. The resulting charge over the switching
period is a current out of V_IN that is typically much larger
than the DC bias current. The gate charge losses are
proportional to V_IN and thus their effects will be more
pronounced at higher supply voltages.
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